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Intel
®
IXP42X product line and IXC1100 control plane processors—SDRAM Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
280 Order Number: 252480-006US
to-data delay will be initialized to two clocks. The initial value in bit 3 will be logic 0. If
a CAS to data delay of three clocks is required, bit 3 of the SDRAM Configuration
(SDR_CONFIG) Register must be set to logic 1.
Bits 2:0 of the SDRAM Configuration (SDR_CONFIG) Register are used to configure the
SDRAM Controller to operate with a given physical memory configuration. Table 108
shows the values that are necessary to be programmed into these register bits for
proper operation.
Additionally, it is physically possible to have different memory configurations and types
attached to the controller than what is written to these registers. Two banks would be
attached when a one-bank configuration is written to SDR_CONFIG and one bank
would be attached when a two-bank configuration is written.
The results are undefined in this case.
Table 107. Memory Configurations for Writing the SDRAM Configuration (SDR_CONFIG)
Register
SDR_CONFIG
[2:0]
Total
memory
64 Mbit 64 Mbit
000 8 Mbyte One chip 2M x32
001 16 Mbyte Two chips 2M x32
010 16 Mbyte Two chips 4M x16
011 32 Mbyte Four chips 4M x16
100 (Reserved)
101 (Reserved)
110 (Reserved)
111 (Reserved)
Notes:
1. Bit 5 of the sdr_config register is set to “1”
2. It is possible to have different values sent to the SDRAM status mode register from what is written to
this register (CAS/RAS latencies). This may result in an undefined operation of the controller.
3. For more detail on the SDRAM Configuration register, see “Configuration Register” on page 287.
Table 108. Memory Configurations for Writing the SDRAM Configuration (SDR_CONFIG)
Register
SDR_CONFIG
[2:0]
Total
memory
128 Mbit 256 Mbit 512 Mbit
000 32 Mbyte Two chips 8 M x16
001 64 Mbyte Four chips 8 M x 16
010 64 Mbyte Two chips 16 M x 16
011 128 Mbyte Four chips 16 M x16
100 128 Mbyte Two chips 32 M x 16
101 256 Mbyte Four chips 32 M x 16
110 Reserved
111 Reserved
Notes:
1. Bit 5 of the sdr_config register is set to “0”
2. It is possible to have different values sent to the SDRAM status mode register from what is written to
this register (CAS/RAS latencies). This may result in an undefined operation of the controller.