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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 167
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
3.9.4.10 Miscellaneous Instruction Timing
3.9.4.11 Thumb Instructions
In general, the timing of Thumb instructions are the same as their equivalent ARM
instructions, except for the cases listed below.
• If the equivalent ARM instruction maps to one in Table 78 on page 162, the
“Minimum Issue Latency with Branch Misprediction” goes from 5 to 6 cycles. This is
due to the branch latency penalty. (See Table 76 on page 160.)
• If the equivalent ARM instruction maps to one in Table 79 on page 162, the
“Minimum Issue Latency when the Branch is Taken” increases by 1 cycle. This is
due to the branch latency penalty. (See Table 76 on page 160.)
• A Thumb BL instruction when H = 0 will have the same timing as an ARM data
processing instruction.
The mapping of Thumb instructions to ARM instructions can be found in the ARM*
Architecture Reference Manual.
3.10 Optimization Guide
3.10.1 Introduction
This document contains optimization techniques for achieving the highest performance
from the IXP42X product line and IXC1100 control plane processors architecture. It is
written for developers who are optimizing compilers or performance analysis tools for
the devices based on these processors. It can also be used by application developers to
obtain the best performance from their assembly language code. The optimizations
presented in this section are based on the IXP42X product line and IXC1100 control
plane processors, and hence can be applied to all products that are based on it.
The IXP42X product line and IXC1100 control plane processors’ architecture includes a
super-pipelined RISC architecture with an enhanced memory pipeline. The IXP42X
product line and IXC1100 control plane processors instruction set is based on the ARM
V5TE architecture; however, the IXP42X product line and IXC1100 control plane
processors include new instructions. Code generated for the SA110, SA1100 and
SA1110 will execute on the IXP42X product line and IXC1100 control plane processors,
however to obtain the maximum performance of your application code, it should be
optimized for the IXP42X product line and IXC1100 control plane processors using the
techniques presented in this document.
Table 91. Exception-Generating Instruction Timings
Mnemonic Minimum latency to first instruction of exception handler
SWI 6
BKPT 6
UNDEFINED 6
Table 92. Count Leading Zeros Instruction Timings
Mnemonic Minimum Issue Latency Minimum Result Latency
CLZ 1 1