Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 15
—Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
18.5.15.6 Bit 5 Reserved...................................................................... 511
18.5.15.7 Bit 6 Reserved...................................................................... 511
18.5.15.8 Transmit Short Packet (TSP) .................................................. 511
18.5.16 UDC Endpoint 14 Control/Status Register (UDCCS14).............................. 512
18.5.16.1 Receive FIFO Service (RFS).................................................... 512
18.5.16.2 Receive Packet Complete (RPC) .............................................. 512
18.5.16.3 Receive Overflow (ROF)......................................................... 512
18.5.16.4 Bit 3 Reserved...................................................................... 512
18.5.16.5 Bit 4 Reserved...................................................................... 512
18.5.16.6 Bit 5 Reserved...................................................................... 512
18.5.16.7 Receive FIFO Not Empty (RNE) ............................................... 513
18.5.16.8 Receive Short Packet (RSP).................................................... 513
18.5.17 UDC Endpoint 15 Control/Status Register (UDCCS15).............................. 514
18.5.17.1 Transmit FIFO Service (TFS)................................................... 514
18.5.17.2 Transmit Packet Complete (TPC)............................................. 514
18.5.17.3 Flush Tx FIFO (FTF)............................................................... 514
18.5.17.4 Transmit Underrun (TUR)....................................................... 514
18.5.17.5 Sent STALL (SST) ................................................................. 515
18.5.17.6 Force STALL (FST) ................................................................ 515
18.5.17.7 Bit 6 Reserved...................................................................... 515
18.5.17.8 Transmit Short Packet (TSP) .................................................. 515
18.5.18 UDC Interrupt Control Register 0 (UICR0).............................................. 516
18.5.18.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7 ........... 516
18.5.19 UDC Interrupt Control Register 1 (UICR1).............................................. 517
18.5.19.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15. ......... 517
18.5.20 UDC Status/Interrupt Register 0 (UISR0)............................................... 518
18.5.20.1 Endpoint 0 Interrupt Request (IR0) ......................................... 519
18.5.20.2 Endpoint 1 Interrupt Request (IR1) ......................................... 519
18.5.20.3 Endpoint 2 Interrupt Request (IR2) ......................................... 519
18.5.20.4 Endpoint 3 Interrupt Request (IR3) ......................................... 519
18.5.20.5 Endpoint 4 Interrupt Request (IR4) ......................................... 519
18.5.20.6 Endpoint 5 Interrupt Request (IR5) ......................................... 519
18.5.20.7 Endpoint 6 Interrupt Request (IR6) ......................................... 520
18.5.20.8 Endpoint 7 Interrupt Request (IR7) ......................................... 520
18.5.21 UDC Status/Interrupt Register 1 (USIR1)............................................... 521
18.5.21.1 Endpoint 8 Interrupt Request (IR8) ......................................... 521
18.5.21.2 Endpoint 9 Interrupt Request (IR9) ......................................... 521
18.5.21.3 Endpoint 10 Interrupt Request (IR10)...................................... 521
18.5.21.4 Endpoint 11 Interrupt Request (IR11)...................................... 521
18.5.21.5 Endpoint 12 Interrupt Request (IR12)...................................... 521
18.5.21.6 Endpoint 13 Interrupt Request (IR13)...................................... 521
18.5.21.7 Endpoint 14 Interrupt Request (IR14)...................................... 521
18.5.21.8 Endpoint 15 Interrupt Request (IR15)...................................... 522
18.5.22 UDC Frame Number High Register (UFNHR) ........................................... 522
18.5.22.1 UDC Frame Number MSB (FNMSB) .......................................... 522
18.5.22.2 Isochronous Packet Error Endpoint 4 (IPE4).............................. 523
18.5.22.3 Isochronous Packet Error Endpoint 9 (IPE9).............................. 523
18.5.22.4 Isochronous Packet Error Endpoint 14 (IPE14) .......................... 523
18.5.22.5 Start of Frame Interrupt Mask (SIM) ....................................... 523
18.5.22.6 Start of Frame Interrupt Request (SIR).................................... 523
18.5.23 UDC Frame Number Low Register (UFNLR) ............................................ 524
18.5.24 UDC Byte Count Register 2 (UBCR2) ..................................................... 524
18.5.24.1 Endpoint 2 Byte Count (BC[7:0]) ............................................ 525
18.5.25 UDC Byte Count Register 4 (UBCR4) ..................................................... 525
18.5.25.1 Endpoint 4 Byte Count (BC[7:0]) ............................................ 525
18.5.26 UDC Byte Count Register 7 (UBCR7) ..................................................... 526
18.5.26.1 Endpoint 7 Byte Count (BC[7:0]) ............................................ 526
18.5.27 UDC Byte Count Register 9 (UBCR9) ..................................................... 526