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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 409
Timers—Intel
®
IXP42X product line and IXC1100 control plane processors
The watch-dog interrupt enable bit enables and disables the interrupt that may be
generated to the IXP42X product line and IXC1100 control plane processors Interrupt
controller when the Watch-Dog Timer Down Counter reaches zero. When the watch-dog
interrupt enable bit is set to logic 1, the Watch-Dog Timer Down Counter will cause an
interrupt to be generated to the Interrupt Controller when the down counter reaches a
value of zero. Writing logic 1 to the associated bit in the watch-dog status register will
clear the interrupt. When the watch-dog interrupt enable bit is set to logic 0, the
Watch-Dog Timer Down Counter will not cause an interrupt to be generated to the
Interrupt Controller when the down counter reaches a value of zero.
The watch-dog reset enable bit enables and disables the watch-dog timer chip reset
capability. The watch-dog timer can be configured to reset the chip after the Watch-Dog
Timer Down Counter reaches zero. If the watch-dog reset enable bit is set to logic 1
and the watch-dog counter down counter reaches a value of zero, a reset signal will be
asserted to the chip causing all register to be set to their associated default values and
the watch-dog timer warm reset bit will be set to a logic 1. The warm reset bit in the
watch-dog status register will signify to the software application that the watch-dog
timer reaching a count of zero caused the last reset event to occur. The warm reset bit
in the watch-dog status register can be cleared by writing logic 1 to the warm reset bit
in the watch-dog status register or the system level reset being asserted.
The watch-dog timer enable bit, watch-dog timer interrupt enable bit, and the watch-
dog timer reset enable bit will be disabled after reset. Therefore, disabling the Watch-
Dog Timer Down Counter. A reset will cause the Watch-Dog Timer Down Counter to
assume a value of all ones.
14.2 Time-Stamp Timer
The time-stamp timer is a readable 32-bit, free-running counter. When reset occurs,
the time-stamp timer is set to all zeros and starts counting up as soon as reset is
released. When the time-stamp timer reaches the maximum value the counter rolls
over to zero and continues to count.
The time-stamp counter will also generate an interrupt signal to the IXP42X product
line and IXC1100 control plane processors’ Interrupt Controller. The time-stamp timer-
interrupt signal contained in the Timer-Status Register can be cleared by a writing a 1
to the associated time-stamp timer interrupt bit in the Timer-Status Register.
14.3 General-Purpose Timers
The two general-purpose timers are composed of a 32-bit, down counter, a one-shot
control bit, a count-enable bit, a 30-bit reload register, and an interrupt-status bit in
the Timer Status Register. The 30-bit, reload register will be used to load the most-
significant 30 bits of the 32-bit, general-purpose timer down counter. The timer will be
reloaded immediately on setting the timer reload register. The least-significant two bits
of the 32-bit, down counter will be loaded with zeros.
The 32-bit, general-purpose down counter will only decrement when the general-
purpose timer control enable bit is set to logic 1. Logic 0 — written to the general-
purpose timer control enable bit — will halt the counting of the 32-bit, general-purpose
down counters.
The general-purpose-timer, one-shot control bit will be utilized to determine the event
that takes place with the general-purpose timer down counter after the counter has
reached a value of 0. The general-purpose, timer down counter can load the 30-bit,
reload value back into the down counter after reaching 0 or the general-purpose, timer
down counter can stop after reaching 0.