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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 73
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
All reads and writes to external memory occur in program order when coalescing is
disabled in the write buffer. If coalescing is enabled in the write buffer, writes may
occur out of program order to external memory. Program correctness is maintained in
this case by comparing all store requests with all the valid entries in the fill buffer.
The write buffer and fill buffer support a drain operation, such that before the next
instruction executes, all Intel XScale processor data requests to external memory have
completed. See Table 18, “Cache Functions” on page 81 for the exact command.
Writes to a region marked non-cacheable/non-bufferable (page attributes C, B, and X
all 0) will cause execution to stall until the write completes.
If software is running in a privileged mode, it can explicitly drain all buffered writes. For
details on this operation, see the description of Drain Write Buffer in “Register 7: Cache
Functions” on page 81.
3.5 Configuration
This section describes the System Control Coprocessor (CP15) and coprocessor 14
(CP14). CP15 configures the MMU, caches, buffers and other system attributes. Where
possible, the definition of CP15 follows the definition of the ARM products. CP14
contains the performance monitor registers, clock and power management registers
and the debug registers.
CP15 is accessed through MRC and MCR coprocessor instructions and allowed only in
privileged mode. Any access to CP15 in user mode or with LDC or STC coprocessor
instructions will cause an undefined instruction exception.
All CP14 registers can be accessed through MRC and MCR coprocessor instructions.
LDC and STC coprocessor instructions can only access the clock and power
management registers, and the debug registers. The performance monitoring registers
can’t be accessed by LDC and STC because CRm != 0x0. Access to all registers is
allowed only in privileged mode. Any access to CP14 in user mode will cause an
undefined instruction exception.
Coprocessors, CP15 and CP14, on the Intel XScale
®
Processor do not support access
via CDP, MRRC, or MCRR instructions. An attempt to access these coprocessors with
these instructions will result in an Undefined Instruction exception.
Many of the MCR commands available in CP15 modify hardware state sometime after
execution. A software sequence is available for those wishing to determine when this
update occurs and can be found in “Additions to CP15 Functionality” on page 153.
Like certain other ARM architecture products, the Intel XScale
®
Processor includes an
extra level of virtual address translation in the form of a PID (Process ID) register and
associated logic. For a detailed description of this facility, see “Register 13: Process ID”
on page 84. Privileged code needs to be aware of this facility because, when interacting
with CP15, some addresses are modified by the PID and others are not.
An address that has yet to be modified by the PID (“PIDified”) is known as a virtual
address (VA). An address that has been through the PID logic, but not translated into a
physical address, is a modified virtual address (MVA). Non-privileged code always deals
with VAs, while privileged code that programs CP15 occasionally needs to use MVAs.
The format of MRC and MCR is shown in Table 7.
cp_num is defined for CP15, CP14 and CP0 on the Intel XScale processor. CP0 supports
instructions specific for DSP and is described in “Programming Model” on page 144