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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
182 Order Number: 252480-006US
3.10.4.2.2 Write-Through and Write-Back Cached Memory Regions
Write through memory regions generate more data traffic on the bus. Therefore is not
recommended that the write-through policy be used. The write back policy must be
used whenever possible.
However, in a multiprocessor environment it will be necessary to use a write through
policy if data is shared across multiple processors. In such a situation all shared
memory regions should use write through policy. Memory regions that are private to a
particular processor should use the write back policy.
3.10.4.2.3 Read Allocate and Read-Write Allocate Memory Regions
Most of the regular data and the stack for your application should be allocated to a
read-write allocate region. It is expected that you will be writing and reading from them
often.
Data that is write only (or data that is written to and subsequently not used for a long
time) should be placed in a read allocate region. Under the read-allocate policy if a
cache write miss occurs a new cache line will not be allocated, and hence will not evict
critical data from the Data cache.
3.10.4.2.4 Creating On-Chip RAM
Part of the Data cache can be converted into fast on chip RAM. Access to objects in the
on-chip RAM will not incur cache miss penalties, thereby reducing the number of
processor stalls. Application performance can be improved by converting a part of the
cache into on chip RAM and allocating frequently allocated variables to it. Due to the
IXP42X product line and IXC1100 control plane processors’ round-robin replacement
policy, all data will eventually be evicted. Therefore to prevent critical or frequently
used data from being evicted it should be allocated to on-chip RAM.
The following variables are good candidates for allocating to the on-chip RAM:
• Frequently used global data used for storing context for context switching.
• Global variables that are accessed in time critical functions such as interrupt service
routines.
The on-chip RAM is created by locking a memory region into the Data cache (see
“Reconfiguring the Data Cache as Data RAM” on page 68 for more details).
When creating the on-chip RAM, care must be taken to ensure that all sets in the on-
chip RAM area of the Data cache have approximately the same number of ways locked,
otherwise some sets will have more ways locked than the others. This uneven
allocation will increase the level of thrashing in some sets and leave other sets under
utilized.
For example, consider three arrays arr1, arr2 and arr3 of size 64 bytes each that are
being allocated to the on-chip RAM and assume that the address of arr1 is 0, address of
arr2 is 1024, and the address of arr3 is 2048. All three arrays will be within the same
sets, i.e. set0 and set1, as a result three ways in both sets set0 and set1, will be
locked, leaving 29 ways for use by other variables.
This can be overcome by allocating on-chip RAM data in sequential order. In the above
example allocating arr2 to address 64 and arr3 to address 128, allows the three arrays
to use only 1 way in sets 0 through 5.