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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 219
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
An access to the IXP42X product line and IXC1100 control plane processors’ PCI
Controller PCI Configuration Registers occurs when the PCI_IDSEL input is asserted,
the PCI command field as represented by the PCI Command/Byte enable signals is a
configuration read or write, PCI_AD[1:0] = 00 indicating a type 0 configuration cycle,
and the PCI Controller Target Interface is allowed to accept Type 0 Configuration Cycles
by asserting the Initialization Complete bit. The PCI Configuration Register accessed is
determined by the value contained on the PCI_AD[7:2] pins during the address phase
of the PCI Configuration Transaction. Accesses to the PCI Configuration Register can be
a single-word only. The PCI Controller Target Interface will disconnect any burst longer
than 1 word.
During reads of the PCI Configuration Registers, byte-enables are ignored and the full
32-bit register value is always returned. Read accesses to unimplemented registers
complete normally on the bus and return all zeroes.
During PCI Configuration Register writes, the PCI byte-enables determine the byte(s)
that are written within the addressed register. Write accesses to unimplemented PCI
Configuration Registers complete normally on the bus but the data is discarded. The
PCI Configuration Space supported by the IXP42X product line and IXC1100 control
plane processors are a single-function, Type 0 configuration space. (For more
information on the PCI Configuration Space and additional configuration details, see
“PCI Configuration Registers” on page 249 and the PCI Local Bus Specification,
Rev. 2.2.)
6.3 Initializing PCI Controller Configuration and Status
Registers for Data Transactions
In order to use the PCI Controller for transactions other than single word initiator
transaction implemented by Non-Pre-fetch transactions, various registers must be set
in the PCI Controller Configuration and Status Registers. The registers that must be
initialized are:
• AHB Memory Base Address Register (PCI_AHBMEMBASE)
• AHB I/O Base Address Register (PCI_AHBIOBASE)
• PCI Memory Base Address Register (PCI_PCIMEMBASE).
The AHB Memory Base Address Register (PCI_AHBMEMBASE) is used to map the
address of a PCI Memory Cycle Target transfers from the address of the PCI Bus to the
address of the South AHB. The AHB I/O Base Address Register (PCI_AHBIOBASE) is
used to map the address of a PCI I/O Cycle Target transfers from the address of the PCI
Bus to the address of the South AHB. The PCI Memory Base Address Register
(PCI_PCIMEMBASE) is used to map the address of direct access PCI memory-mapped
transfers from the address of the South AHB to the address of the PCI Bus.
When the IXP42X product line and IXC1100 control plane processors are the target of a
PCI bus transaction, the values written or read by external PCI Bus Initiators using the
Base Address Registers contained within the IXP42X product line and IXC1100 control
plane processors must be translated to an address location within the IXP42X product
line and IXC1100 control plane processors. The configuration of the internal memory
allocation is implemented differently for each of the Base Address Registers (BAR). The
following paragraphs describe the implementation for each of the Base Address
Registers.
For Base Address Registers 0 through 3 — which are used to complete PCI Bus Memory
Cycles Target transactions — the AHB Memory Base Address (PCI_AHBMEMBASE)
register is used to translate PCI Memory Cycle accesses to their appropriate AHB
locations. The AHB Memory Base Address (PCI_AHBMEMBASE) register is used to
determine the upper 8 AHB address bits when an external Initiator on the PCI bus
accesses the memory spaces of the IXP42X product line and IXC1100 control plane