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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 535
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
18.5.41 UDC Data Register 11
(UDDR11)
Endpoint 11 is a double-buffered, bulk IN endpoint that is 64 bytes deep. Data can be
loaded via direct Intel XScale
®
processor writes.
Because it is double-buffered, up to two packets of data may be loaded for
transmission.
18.5.42 UDC Data Register 12 (UDDR12)
Endpoint 12 is a double-buffered, bulk OUT endpoint that is 64 bytes deep. The UDC
will generate an interrupt request as soon as the EOP is received.
Since it is double-buffered, up to two packets of data may be ready. Via direct read
from the Intel XScale
®
processor, the data can be removed from the UDC. If one
packet is being removed and the packet behind it has already been received, the UDC
will issue a NAK to the host the next time it sends an OUT packet to endpoint 12.
This NAK condition will remain in place until a full packet space is available in the UDC
at Endpoint 12.
Register Name: UDDR11
Hex Offset Address: 0 x C800BB00 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 11 Data Register
Access: Write
Bits
31 87 0
(Reserved) (8-Bit Data)
X 00000000
Resets (Above)
Register
UDDR11
Bits Name Description
31:8 Reserved for future use.
7:0 DATA Top of endpoint data currently being loaded.
Register Name: UDDR12
Hex Offset Address: 0 x C800BB80 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 12 Data Register
Access: Read
Bits
31 87 0
(Reserved) (8-Bit Data)
X 00000000
Resets (Above)