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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 519
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
The bits in USIR0 and USIR1 are controlled by a mask bit in the UDC Interrupt Control
Register (UICR0/1). The mask bits, when set, prevent a status bit in the USIRx from
being set. If the mask bit for a particular status bit is cleared and an interruptible
condition occurs, the status bit is set.
To clear status bits, the Intel XScale
®
processor must write a 1 to the position to be
cleared. The interrupt request for the UDC remains active as long as the value of the
USIRx is non-zero.
18.5.20.1 Endpoint 0 Interrupt Request (IR0)
The endpoint 0 interrupt request is set if the IM0 bit in the UDC control register is
cleared and, in the UDC endpoint 0 control/status register, the OUT packet ready bit is
set, the IN packet ready bit is cleared, or the sent STALL bit is set. The IR0 bit is
cleared by writing a 1 to it.
18.5.20.2 Endpoint 1 Interrupt Request (IR1)
The interrupt request bit is set if the IM1 bit in the UDC interrupt control register is
cleared and the IN packet complete (TPC) in UDC endpoint 1 control/status register is
set.
The IR1 bit is cleared by writing a 1 to it.
18.5.20.3 Endpoint 2 Interrupt Request (IR2)
The interrupt request bit is set if the IM2 bit in the UDC Interrupt Control Register is
cleared and the OUT packet ready bit (RPC) in the UDC Endpoint 2 Control/Status
Register is set.
The IR2 bit is cleared by writing a 1 to it.
18.5.20.4 Endpoint 3 Interrupt Request (IR3)
The interrupt request bit is set if the IM3 bit in the UDC Interrupt Control Register is
cleared and the IN packet complete (TPC) or Transmit Underrun (TUR) in UDC Endpoint
3 Control/Status Register is set.
The IR3 bit is cleared by writing a 1 to it
18.5.20.5 Endpoint 4 Interrupt Request (IR4)
The interrupt request bit is set if the IM4 bit in the UDC Interrupt Control Register is
cleared and the OUT packet ready (RPC) or receiver overflow (ROF) in the UDC
Endpoint 4 Control/Status Register or the Isochronous Error Endpoint 4 (IPE4) in the
UFNHR are set.
The IR4 bit is cleared by writing a 1 to it.
18.5.20.6 Endpoint 5 Interrupt Request (IR5)
The interrupt request bit is set if the IM5 bit in the UDC Interrupt Control Register is
cleared and the IN packet complete (TPC) in UDC Endpoint 5 Control/Status Register is
set.
The IR5 bit is cleared by writing a 1 to it.