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Intel
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IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 437
Ethernet MAC A—Intel
®
IXP42X product line and IXC1100 control plane processors
15.2.24 Address Mask Registers
Six registers make up the 48-bit Address Mask:
• Address Mask[47:40] — Address Mask 1
• Address Mask[39:32] — Address Mask 2
• Address Mask[31:24] — Address Mask 3
• Address Mask[23:16] — Address Mask 4
• Address Mask[15:8] — Address Mask 5
• Address Mask[7:0] — Address Mask 6
Example: Address Mask is 00-A0-24-D1-7F-02
• Address Mask 1 = 0x00
• Address Mask 2 = 0x00
• Address Mask 3 = 0x00
• Address Mask 4 = 0xFF
• Address Mask 5 = 0xFF
• Address Mask 6 = 0x00
The detailed bit descriptions follow the six registers’ bit maps.
15.2.25 Address Mask 1
Register MDIO Status
Bits Name Description
31 Successful read
0 = A successful read
1= A read error.
Read only.
30:16 (Reserved) Read only.
15:0 Read data Read only.
Register Name: addrmask1
Hex Offset Address: 0x C80090A0 Reset Hex Value: 0x00000000
Register
Description:
Address Mask Register #1. First register of six that makes up the Address Mask. Address Mask is used
with Address for multicast address filtering. Bits set to 1 in Address Mask represent bits of the Address
Register that must match the corresponding bits in incoming destination addresses for packets to be
accepted
Access: Read/Write.
31 87 0
(Reserved) ADDRESS MASK[7:0]