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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
56 Order Number: 252480-006US
The entire instruction cache along with the fetch buffers are invalidated by writing to
coprocessor 15, register 7. (See Table 18, “Cache Functions” on page 81 for the exact
command.) The invalidate command does not unlock any lines that were locked in the
instruction cache nor does it invalidate those locked lines. To invalidate the entire cache
including locked lines, the unlock instruction cache command needs to be executed
before the invalidate command. The unlock command can also be found in Table 20,
“Cache Lock-Down Functions” on page 83.
There is an inherent delay from the execution of the instruction cache invalidate
command to where the next instruction will see the result of the invalidate. The
following routine can be used to guarantee proper synchronization.
The Intel XScale processor also supports invalidating an individual line from the
instruction cache. See Table 18, “Cache Functions” on page 81 for the exact command.
Software has the ability to lock performance critical routines into the instruction cache.
Up to 28 lines in each set can be locked; hardware will ignore the lock command if
software is trying to lock all the lines in a particular set (i.e., ways 28-31can never be
locked). When all ways in a particular set are requested to be locked, the instruction
cache line will still be allocated into the cache but the lock will be ignored. The round-
robin pointer will stay at way 31 for that set.
Cache lines can be locked into the instruction cache by initiating a write to
coprocessor 15. (See Table 20, “Cache Lock-Down Functions” on page 83 for the exact
command.) Register Rd contains the virtual address of the line to be locked into the
cache.
There are several requirements for locking down code:
• The routine used to lock lines down in the cache must be placed in non-cacheable
memory, which means the MMU is enabled.
Example 5. Enabling the Instruction Cache
; Enable the ICache
MRC P15, 0, R0, C1, C0, 0 ; Get the control register
ORR R0, R0, #0x1000 ; set bit 12 -- the I bit
MCR P15, 0, R0, C1, C0, 0 ; Set the control register
CPWAIT
Example 6. Invalidating the Instruction Cache
MCR P15,0,R1,C7,C5,0 ; Invalidate the instruction cache and branch
; target buffer
CPWAIT
; The instruction cache is guaranteed to be invalidated at this point; the next
; instruction sees the result of the invalidate command.