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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 247
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
There is no byte-lane reversal process for accesses to PCI Controller Configuration and
Status Registers or PCI Configuration Registers. Figure 52 shows the byte-lane routing
for these types of accesses.
For example, a PCI Configuration Register write from an external PCI Device, with byte
enable 2 asserted, will write to bits 23:16 of the addressed register. An AHB write with
Address bits [1:0] = 10b — while being configured in big-endian mode (pci_csr.ABE =
1) of operation — will write bits 15:8 of an addressed PCI Controller Configuration and
Status Register. When the AHB is configured in little-endian mode (pci_csr.ABE = 0) of
operation, bits 23:16 of the same addressed PCI Controller Configuration and Status
Register will be written.
Figure 51. Byte Lane Routing During DMA Transfers
31
24
AHB-to-PCI DMA,
DS = 1
AHB Data
3
2
1
0
23
16
15
8
7
0
31
24
00 01
10
11
23
16
15
8
7
0
31
24
3 2
1
0
23
16
15
8
7
0
31
24
00 01
10
11
23
16
15
8
7
0
AHB Data
PCI Data PCI Data
PCI-to-AHB DMA,
DS = 1
31
24
AHB-to-PCI DMA,
DS = 0
AHB Data
3
2
1
0
23
16
15
8
7
0
31
24
00 01
10
11
23
16
15
8
7
0
31
24
3 2
1
0
23
16
15
8
7
0
31
24
00 01
10
11
23
16
15
8
7
0
AHB Data
PCI Data PCI Data
PCI-to-AHB DMA,
DS = 0