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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
502 Order Number: 252480-006US
18.5.11 UDC Endpoint 9 Control/Status Register (UDCCS9)
The UDC Endpoint 9 Control/Status Register contains six bits that are used to operate
endpoint 9, an isochronous OUT endpoint.
18.5.11.1 Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
256 bytes, a short packet, or a zero packet. UDCCS9[RFS] is not cleared until all data is
read from both buffers.
18.5.11.2 Receive Packet Complete (RPC)
The receive packet complete bit gets set by the UDC when an OUT packet is received.
When this bit is set, the IR9 bit in the appropriate UDC status/interrupt register is set if
receive interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 9 Control/
Status Register. The UDCCS9[RPC] bit is cleared by writing a 1 to it.
18.5.11.3 Receive Overflow (ROF)
The receive overflow bit generates an interrupt on IR9 in the appropriate UDC status/
interrupt register to alert the software that Isochronous data packets are being
dropped because neither FIFO buffer has room for them. This bit is cleared by writing a
1 to it.
18.5.11.4 Bit 3 Reserved
Bit 3 is reserved for future use.
18.5.11.5 Bit 4 Reserved
Bit 4 is reserved for future use.
18.5.11.6 Bit 5 Reserved
Bit 5 is reserved for future use.
18.5.11.7 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that the receive FIFO has unread data in it.
When the UDCCS9[RPC] bit is set, this bit must be read to determine if there is any
data in the FIFO that Intel XScale
®
processor did not read.
The receive FIFO must continue to be read until this bit clears or data will be lost.
18.5.11.8 Receive Short Packet (RSP)
The receive short packet bit is used by the UDC to indicate that the received OUT
packet in the active buffer currently being read is a short packet or zero-sized packet.
This bit is updated by the UDC after the last byte is read from the active buffer and
reflects the status of the new active buffer.
If UDCCS9[RSP] is a one and UDCCS9[RNE] is a 0, it indicates a zero-length packet. If
a zero-length packet is present, the Intel XScale
®
processor must not read the data
register.