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Intel
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IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
238 Order Number: 252480-006US
Assume that this DMA channel is enabled prior to the end of the first eight-word
burst of the first write DMA transfer ending. The DMA read transfer to the PCI bus
becomes interleaved with the first write transfer. So the first eight words of the
read starts towards completion.
7. Update the AHB to PCI DMA Length Register 1 (PCI_ATPDMA1_LENGTH) with
PCI_ATPDMA1_LENGTH = 0x90000006.
Assume this is set while the above read DMA transaction is occurring.
8. The next PCI transfer is completing the last eight words of the initial 16-word write
DMA transfer. That is followed by the last eight words of the 16-word read DMA
transfer and the execution of the six-word write transfer with the data byte lanes
swapped.
6.8.1 AHB to PCI DMA Channel Operation
The AHB-to-PCI (ATP) channel uses the PCI Core Initiator Request and Initiator
Transmit FIFOs. The channel reads data from the AHB bus and writes it to a PCI target
on word-aligned boundaries.
A DMA transfer from AHB to PCI is processed as follows:
1. An AHB master writes the PCI starting address, AHB starting address, and word
count to the PCI_ATPDMA0/1_PCIADDR, PCI_ATPDMA0/1_AHBADDR,
PCI_ATPDMA0/1_LENGTH registers respectively. If the channel enable bit is set in
the PCI_ATPDMA0/1_LENGTH register, the DMA transfer commences.
2. The DMA Controller signals the AHB Slave Interface to retry all access attempts
from the AHB bus and waits for any AHB accesses of the PCI Bus to complete.
3. The DMA Controller signals the AHB Master Interface to stop servicing requests
from the PCI bus, and waits for any pending accesses from PCI to complete.
4. When access is obtained, data is read from AHB and loaded into the Initiator
Transmit FIFO. A PCI write request is loaded into the Initiator Request FIFO.
5. When the transfer completes on the PCI bus, the DMA address and length registers
are updated.
6. Steps 4-6 are repeated until all data is transfered. Once the DMA Controller gets
control of the hardware, the DMA channel reads from AHB and writes to PCI 8
words at a time until the transfer is done or 1) an AHB or PCI access is attempted
or 2) the other DMA channel has a transfer enabled. In the case of 1) or 2), the
DMA channel will release the resources, then go to step 2 where it re-requests
access to these resources to continue the transfer. When done, the channel enable
bit in the PCI_ATPDMA0/1_LENGTH register is cleared, the DMA complete status bit
is set and — if enabled — an interrupt is asserted on PCC_ATPDMA_INT AND/OR
PCC_INT. PCC_PTADMA_INT and PCC_INT are signal internal to the IXP42X product
line and IXC1100 control plane processors and are routed to the Interrupt
Controller.
7. In response to the interrupt, an AHB agent may read the DMA Control register
(PCI_DMACTRL) to determine the status of the transfer.
6.8.2 PCI to AHB DMA Channel Operation
The PCI to AHB (PTA) channel uses the PCI Core Initiator Request and Initiator Receive
FIFOs. The channel reads data from the PCI bus and writes it to an AHB slave on word-
aligned boundaries.
A DMA transfer from PCI to AHB is processed as follows:
1. An AHB master writes the PCI starting address, AHB starting address, and word
count to the PCI_PTADMA0/1_PCIADDR, PCI_PTADMA0/1_AHBADDR,