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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 161
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
• Cycle Distance from A to B
The cycle distance from cycle A to cycle B is (B-A) -- that is, the number of cycles
from the start of cycle A to the start of cycle B. Example: the cycle distance from
cycle 3 to cycle 4 is one cycle.
• Issue Latency
The cycle distance from the first issue clock of the current instruction to the issue
clock of the next instruction. The actual number of cycles can be influenced by
cache-misses, resource-dependency stalls, and resource availability conflicts.
• Result Latency
The cycle distance from the first issue clock of the current instruction to the issue
clock of the first instruction that can use the result without incurring a resource
dependency stall. The actual number of cycles can be influenced by cache-misses,
resource-dependency stalls, and resource availability conflicts.
• Minimum Issue Latency (without Branch Misprediction)
The minimum cycle distance from the issue clock of the current instruction to the
first possible issue clock of the next instruction assuming best case conditions (i.e.,
that the issuing of the next instruction is not stalled due to a resource dependency
stall; the next instruction is immediately available from the cache or memory
interface; the current instruction does not incur resource dependency stalls during
execution that can not be detected at issue time; and if the instruction uses
dynamic branch prediction, correct prediction is assumed).
• Minimum Result Latency
The required minimum cycle distance from the issue clock of the current
instruction to the issue clock of the first instruction that can use the result without
incurring a resource dependency stall assuming best case conditions (i.e., that the
issuing of the next instruction is not stalled due to a resource dependency stall; the
next instruction is immediately available from the cache or memory interface; and
the current instruction does not incur resource dependency stalls during execution
that can not be detected at issue time).
• Minimum Issue Latency (with Branch Misprediction)
The minimum cycle distance from the issue clock of the current branching
instruction to the first possible issue clock of the next instruction. This definition is
identical to Minimum Issue Latency except that the branching instruction has been
incorrectly predicted. It is calculated by adding Minimum Issue Latency (without
Branch Misprediction) to the minimum branch latency penalty number from
Table 76, which is four cycles.
• Minimum Resource Latency
The minimum cycle distance from the issue clock of the current multiply instruction
to the issue clock of the next multiply instruction assuming the second multiply
does not incur a data dependency and is immediately available from the instruction
cache or memory interface.
For the following code fragment, here is an example of computing latencies:
Table 77 shows how to calculate Issue Latency and Result Latency for each instruction.
Looking at the issue column, the UMLAL instruction starts to issue on cycle 0 and the
next instruction, ADD, issues on cycle 2, so the Issue Latency for UMLAL is two. From
Example 20. Computing Latencies
UMLALr6,r8,r0,r1
ADD r9,r10,r11
SUB r2,r8,r9
MOV r0,r1