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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 281
SDRAM Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
An example of configuring the SDRAM Configuration (SDR_CONFIG) Register is shown
below:
1. Assume that the application being configured is a 256-Mbyte configuration using
four chips (32 Mbyte x 16) and a CAS to data delay of three clocks. See Figure 54
for an SDRAM Connection Example of a similar configuration.
2. A hexadecimal value of 0x0000000Dis written to 0xCC000000.
The SDRAM Refresh (SDR_REFRESH) Register is used to determine the number of
cycles before a mandatory refresh command is issued. The SDRAM Refresh
(SDR_REFRESH) Register is a 16-bit register that is used to determine the termination
count of the automatic refresh command. The counter used to implement the
automatic refresh timer is 16 bits operating at 133 MHz. The counter size allows a
maximum of 492 microseconds between mandatory refreshes.
When a hexadecimal value of 0x00000000 is programmed to this register, the
automatic refresh capability of the SDRAM Controller will be disabled. When an
automatic refresh is performed, the valid bits of the open page registers will be
“invalid.” In addition, when the refresh timer expires and the SDRAM Controller issues
an auto-refresh command, all pages are closed.
If the SDRAM controller is idle when the auto-refresh timer expires, the SDRAM
Controller initiates the refresh operation the next clock after detecting a refresh
request. If the SDRAM controller is busy processing a read or write transaction, the
SDRAM Controller does not initiate the refresh operation until it completes the previous
transaction. The default value of the SDRAM Refresh (SDR_REFRESH) Register is
hexadecimal 0x0384.
An example of how to use the SDRAM Refresh (SDR_REFRESH) Register is shown
below:
1. Assume that the application being configured requires an automatic refresh time of
hexadecimal 0x00001AB5.
2. A hexadecimal value of 0x00001AB5 is written to 0xCC000004. Therefore a refresh
would occur about every 51.4 microseconds.
The SDRAM Instruction (SDR_IR) Register is used to provide specific commands to the
SDRAM that can be useful in configuration of the SDRAM initialization and operation.
The SDRAM Instruction (SDR_IR) Register is a 3-bit register that contains a command
decode. Table 109 shows the commands that can be used to produce specific operation
over the SDRAM interface.
Table 109. SDRAM Command Description (Sheet 1 of 2)
Command Name
SDR_IR[2:
0]
Description
Mode-Register-Set 000
Produces SDRAM cycles that set the SDRAM mode register with a CAS to
data delay of 2, a write burst mode set to single location access
(meaning reads will be use the burst length value and writes will be
single location access), an operating mode set to standard operation, a
burst type set to sequential, and a burst length set to a value of 8.
Mode-Register-Set 001
Produces SDRAM cycles that set the SDRAM mode register with a CAS to
data delay of 3, a write burst mode set to single location access
(meaning reads will be use the burst length value and writes will be
single location access), an operating mode set to standard operation, a
burst type set to sequential, and a burst length set to a value of 8.
Precharge-All 010
Used to pre-charge all banks of memory. A pre-charge is used to close all
open banks of memory.
NOP 011
A command used to produce a null command to the SDRAM. This
command is used during initialization and can be used to filter any
spurious commands during idle or wait states.