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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
84 Order Number: 252480-006US
3.5.1.12 Register 11-12: Reserved
These registers are reserved. Reading and writing them yields unpredictable results.
3.5.1.13 Register 13: Process ID
The Intel XScale processor supports the remapping of virtual addresses through a
Process ID (PID) register. This remapping occurs before the instruction cache,
instruction TLB, data cache and data TLB are accessed. The PID register controls when
virtual addresses are remapped and to what value.
The PID register is a 7-bit value that is ORed with bits 31:25 of the virtual address
when they are zero. This action effectively remaps the address to one of 128 “slots” in
the 4 Gbytes of address space. If bits 31:25 are not zero, no remapping occurs. This
feature is useful for operating system management of processes that may map to the
same virtual address space. In those cases, the virtually mapped caches on the Intel
XScale processor would not require invalidating on a process switch.
3.5.1.14 The PID Register Affect On Addresses
All addresses generated and used by User Mode code are eligible for being “PIDified” as
described in the previous section. Privileged code, however, must be aware of certain
special cases in which address generation does not follow the usual flow.
The PID register is not used to remap the virtual address when accessing the Branch
Target Buffer (BTB). Any writes to the PID register invalidate the BTB, which prevents
any virtual addresses from being double mapped between two processes.
A breakpoint address (see “Register 14: Breakpoint Registers” on page 85) must be
expressed as an MVA when written to the breakpoint register. This requirement means
the value of the PID must be combined appropriately with the address before it is
written to the breakpoint register. All virtual addresses in translation descriptors (see
“Memory Management Unit” on page 44) are MVAs.
Translate and Lock D TLB entry 0b000 0b1000 MVA MCR p15, 0, Rd, c10, c8, 0
Unlock I TLB 0b001 0b0100 Ignored MCR p15, 0, Rd, c10, c4, 1
Unlock D TLB 0b001 0b1000 Ignored MCR p15, 0, Rd, c10, c8, 1
Table 22. TLB Lockdown Functions
Function opcode_2 CRm Data Instruction
Table 23. Accessing Process ID
Function opcode_2 CRm Instruction
Read Process ID Register 0b000 0b0000 MRC p15, 0, Rd, c13, c0, 0
Write Process ID Register 0b000 0b0000 MCR p15, 0, Rd, c13, c0, 0
Table 24. Process ID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Process ID
reset value: 0x0000,0000
Bits Access Description
31:25 Read / Write
Process ID - This field is used for remapping the virtual
address when bits 31-25 of the virtual address are zero.
24:0 Read-as-Zero / Write-as-Zero
Reserved - Should be programmed to zero for future
compatibility