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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 333
Universal Asynchronous Receiver Transceiver (UART)—Intel
®
IXP42X product line and IXC1100
control plane processors
10.1 High Speed UART
The UARTs performs serial-to-parallel conversion — on data characters received from a
peripheral device or a modem — and parallel-to-serial conversion — on data characters
received from the Intel XScale
®
Processor.
The Intel XScale processor, within the Intel
®
IXP42X product line and IXC1100 control
plane processors, can read the complete status of the UART at any time during
functional operation. Available status information includes the type and condition of the
transfer operations being performed by the UART, as well as any detected error
conditions (such as parity, overrun, framing, or break interrupt).
The UART is compatible with the 16550 UART specification, with enhancements in place
to support higher speeds than defined by the 16550 UART specification. The UARTs
are capable of supporting data transfers containing five, six, seven, or eight data bits.
The data transfers may be configured to have one or two stop bits and supports even,
odd, or no parity.
Figure 78 shows a functional waveform of the data that could be contained on the UART
transmit and receive lines. Notice that Data bits 5 through 7, the Parity Bit, and Stop
Bit 2 are shaded. The Data bits 5 through 7, Parity Bit, and Stop Bit 2 are all
programmable and optional as previously described.
The serial port can operate in either FIFO or non-FIFO mode. In FIFO mode, a 64-byte
transmit FIFO holds data coming from the Intel XScale processor to be transmitted on
the serial link, and the 64-byte Receive FIFO, buffers data received from the serial link
until the data is read by the Intel XScale processor.
The UARTs include a programmable baud rate generator capable of dividing the
14.7456-MHz, UART input clock by divisors of 1 to (2
16
–1) and produces a 16X clock to
drive the internal transmitter and receiver logic. The 14.7456-MHz, UART input clock is
generated internally to the IXP42X product line and IXC1100 control plane processors.
Interrupts can be programmed to the user’s requirements, minimizing the computing
required to handle the communications link. Each UART can be operated in a polled or
an interrupt driven environment as selected by software.
The maximum baud rate supported by the High-Speed UART and Console UART is
921.6 Kbps. The divisors programmed in divisor latch registers should be equal to or
greater than 1 for proper operation.
The device UARTs may be initialized by setting 13 configuration registers.
Figure 79 shows a functional block diagram of the UART interface.
Figure 78. UART Timing Diagram
Start
Dat
a
<0>
Dat
a
<1>
Dat
a
<2>
Dat
a
<3>
Dat
a
<4>
Dat
a
<5>
Data
<6>
Data
<7>
Parity
Bit
Stop
Bit 1
Stop
Bit 2
LSB MSB
UART
TXD or RXD
Bit Definition