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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 337
Universal Asynchronous Receiver Transceiver (UART)—Intel
®
IXP42X product line and IXC1100
control plane processors
The Even-Parity Select (EPS) Bit is used to determine the parity type to transmit or
check on receive data when the Parity-Enable (PEN) Bit in the Line-Control Register
enables parity. When the Parity-Enable bit is logic 1 and the Even-Parity Select bit is
logic 0, the parity generator will transmit odd parity and the parity checker will validate
against odd parity on the received data.
When the Parity-Enable Bit is logic 1 and the Even-Parity Select Bit is logic 1, the parity
generator will transmit even parity and the parity checker will validate against even
parity on the received data.
Table 130 shows the serial output data configurations for transmission of the parity bit.
Table 131 shows the serial input data configurations for reception of data containing a
parity bit:
The Stop-Bits Bit (STB) configures the number of stop bits to be transmitted or
received in each serial character. When the Stop-Bits Bit is logic 0, one stop bit is
generated in the transmitted data. When the Stop-Bits Bit is logic 1, and a 5-bit word
length is selected — via the Word Length select bits in the Line Control Register — 1.5
stop bits will be transmitted.
When the Stop-Bits Bit is logic 1 and the word length is selected as a 6, 7, or 8-bit
word, 2 stop bits are transmitted. The UART receiver logic checks the first stop bit only,
regardless of the number of stop bits configured by the Stop Bits bit.
The Word-Length Select (WLS) Bits specify the number of data bits contained in each
transmitted or received serial character. The Word-Length Select Bits configuration is
shown in Table 132.
Table 130. UART Transmit Parity Operation
PEN EPS
Data to be Transmitted
(Even or Odd Count of 1s to be Transmitted)
Value of Parity Bit to be
Transmitted
1 0 10101010 1
1 0 10101011 0
1 1 10101010 0
1 1 10101011 1
0 X XXXXXXXX No Parity Bit Sent
Table 131. UART Receive Parity Operation
PEN EPS
Data beIng Received + Parity Bit
(Even or Odd Count of 1s to be Transmitted)
Value of Parity Bit Should Be
1 0 101010101 1
1 0 101010110 0
1 1 101010100 0
1 1 101010111 1
0 X XXXXXXXX Parity Checking Disabled