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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 405
Interrupt Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
13.5.6 Interrupt Priority Register
13.5.7 IRQ Highest-Priority Register
Register Name: INTR_PRTY
Hex Offset Address: 0xC800 3014 Reset Hex Value: 0x00FAC688
Register
Description:
The highest eight priority interrupts can be programmed via this register, each of the 3-bit sets can be
programmed to any priority from 0(000) through 7(111). This register applies to both IRQ and FIQ
interrupts.
Access: Read/Write.
31 24 23 0
Undefined/Zero Interrupt Priority selects
Register
INTR_PRTY
Bits Name Description
31 Zero Read as undefined, write as 0
30 Zero Read as undefined, write as 0
29 Zero Read as undefined, write as 0
28 Zero Read as undefined, write as 0
27 Zero Read as undefined, write as 0
26 Zero Read as undefined, write as 0
25 Zero Read as undefined, write as 0
24 Zero Read as undefined, write as 0
23:21 Prior_Intbus7 [2:0] Set the priority of the Intr_bus [7]; default is 7
20:18 Prior_Intbus6 [2:0] Set the priority of the Intr_bus [6]; default is 6
17:15 Prior_Intbus5 [2:0] Set the priority of the Intr_bus [5]; default is 5
14:12 Prior_Intbus4 [2:0] Set the priority of the Intr_bus [4]; default is 4
11:9 Prior_Intbus3 [2:0] Set the priority of the Intr_bus [3]; default is 3
8:6 Prior_Intbus2 [2:0] Set the priority of the Intr_bus [2]; default is 2
5:3 Prior_Intbus1 [2:0] Set the priority of the Intr_bus [1]; default is 1
2:0 Prior_Intbus0 [2:0] Set the priority of the Intr_bus [0]; default is 0
Register Name: INTR_IRQ_ENC_ST
Hex Offset Address: 0xC800 3018 Reset Hex Value: 0x00000000
Register
Description:
This register returns the “incremented number” of the highest-priority interrupt that is pending for the
IRQ. For example, if interrupt 0 is the highest IRQ pending, the register returns 1. If the register returns
0, it means that there is no interrupt pending or a spurious interrupt.
Note that the encoded number is shifted left by two bits, a software requirement for the value to be
multiplied by 4 before being read.
Access: Read.
31 87 210
(Undefined) IRQ_ENC_ST RES