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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 463
High-Speed Serial Interfaces—Intel
®
IXP42X product line and IXC1100 control plane
processors
The HSS interface can be programmed to automatically ignore (lookup table assigned)
the last eight timeslots meaning the NPE will not receive the contents of the last eight
timeslots. When timeslot 23 is transmitted, the next data from the NPE will not be
transmitted until timeslot zero occurs. The HSS will transmit all zeros/ones for the
duration of the empty timeslots (NPE programmable).
The NPE must program the HSS to indicate which method of T1 mapping is used (if
any).
17.6.3.2 MVIP Using 4.096-Mbps Backplane
This backplane is used to transport 2 E1s or 2 T1s on a single line utilizing a clock rate
of 4.096 MHz. Two complete E1 frames will fill this frame, therefore unassigned
timeslots are not compulsory. When transporting T1 frames, unassigned timeslots are
used for padding the frame due to the shorter length of the T1 frame.
Figure 91. MVIP, Frame Mapping a T1 Frame to an E1 Frame
0
012345670123456FBit
6543210765
012345678910
11
12 13 14
15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Timeslot
Bits
Unused timeslots
31 0
2.048
MHz clock
Frame pulse
1234
56
7
Figure 92. MVIP, Byte Interlacing Two E1 Streams Onto a 4.096-Mbps Backplane
0 0123456701234567654321076 7
0a
0b 1a 1b 2a 2b
3a
3b 4a 4b 5a 5b 6a 6b 7a 7b 8a 8b
9a
9b 10a 10b 11a 11b 12a 12b 13a 13b 14a 14b 15a 15b
Timeslots
Bits
31b 16a
4. 096
MHz clock
Frame pulse
1234567