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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 239
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
PCI_PTADMA0/1_LENGTH registers respectively. If the channel enable bit is set in
the PCI_PTADMA0/1_LENGTH register, the DMA transfer commences.
2. The DMA Controller signals the AHB Slave Interface to retry all access attempts
from the AHB bus and waits for any pending AHB accesses of the PCI Bus to
complete.
3. The DMA Controller signals the AHB Master Interface to stop servicing requests
from the PCI bus, and waits for any pending accesses from PCI to complete
4. The DMA Controller issues a read request to the PCI Core via the Request FIFO.
5. When the PCI data arrives in the Initiator Receive FIFO, the data is written to the
AHB Bus.
6. When the transfer completes on the AHB bus, the DMA address and length
registers are updated.
7. Steps 4-6 are repeated. Once the DMA Controller gets control of the hardware, the
DMA channel reads from the PCI Bus and write to the AHB Bus 8 words at a time
until the transfer is done or 1) an AHB or PCI access is attempted or 2) the other
DMA channel has a transfer enabled. In the case of 1) or 2) above, the currently
active DMA channel will release the resources, then go to step 2 where it re-
requests access to these resources to continue the transfer. When done, the
channel enable bit in the PCI_PTADMA0/1_LENGTH register is cleared, the DMA
complete status bit is set and, if enabled, an interrupt is asserted on
PCC_PTADMA_INT and/or PCC_INT. PCC_PTADMA_INT and PCC_INT are signal
internal to the IXP42X product line and IXC1100 control plane processors and are
routed to the Interrupt Controller.
8. In response to the interrupt, an AHB agent may read the DMA Control register
(PCI_DMACTRL) to determine the status of the transfer.
6.9 PCI Controller Door Bell Register
The PCI Controller has two registers that make up the Door Bell register logic on the
IXP42X product line and IXC1100 control plane processors. These two registers are the
AHB Door Bell (PCI_AHBDOORBELL) register and the PCI Door Bell Register
(PCI_PCIDOORBELL).
An external PCI device writes the AHB Door Bell (PCI_AHBDOORBELL) register to
generate an interrupt signal to the Intel XScale processor. If the AHB doorbell interrupt
is enabled (PCI_INTEN.ADBEN = 1) in the PCI interrupt registers, any bit set to logic 1
in the AHB Door Bell (PCI_AHBDOORBELL) will force the interrupt signal to occur.
The AHB Door Bell (PCI_AHBDOORBELL) register is set from the PCI bus only by writing
logic 1 to the register. Writing logic 1 to the set bits from the SOUTH AHB clears bits
that are set in the AHB Door Bell (PCI_AHBDOORBELL).
An example of using the AHB Door Bell (PCI_AHBDOORBELL) is as follows:
1. An external PCI device writes logic 1 to a bit or pattern of bits to generate an
interrupt to the Intel XScale processor.
2. The AHB agent reads the AHB Door Bell (PCI_AHBDOORBELL) register and writes
logic 1(s) to all set bits clear the set bit(s). This in turn de-assert the interrupt
generated to the Intel XScale processor.
Using the South AHB, the Intel XScale processor writes the PCI Door Bell Register
(PCI_PCIDOORBELL) to generate an interrupt to an external PCI device over the
PCI_INTA_N signal. Any bit set to logic 1 in the PCI Door Bell Register
(PCI_PCIDOORBELL) will generate the PCI interrupt if the PCI doorbell interrupt is
enabled the PCI Interrupt Enable Register (PCI_INTEN).