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IXP42X product line and IXC1100 control plane processors—Overview of Product Line
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
40 Order Number: 252480-006US
communicated to the NPEs via the flag bus. Combined queue status for queues 32-63
are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-
31 and one for queues 32-63, provide status interrupts to the Intel XScale processor.
For more information on the AHB Queue Manager, see Section 21.0, “AHB Queue
Manager (AQM)” on page 556.
2.6 UTOPIA 2
The integrated UTOPIA Level -2 interface has a dedicated network-processing engine.
The interface allows a multiple- or single-physical-interface configuration. The network
processing engine handles segmentation and reassembly of Asynchronous Transfer
Mode (ATM) cells, CRC Checking/Generation, and the transfer of data to and from
memory. This enables parallel processing of data traffic on the UTOPIA Level-2
interface, off loading processor overhead required by the Intel XScale processor.
The IXP42X product line and IXC1100 control plane processors are compliant with the
ATM Forum, UTOPIA Level -2, Revision 1.0 specification.
For more information on the UTOPIA Level-2 interface, see Section 19.0, “UTOPIA
Level-2” on page 538.
2.7 USB v1.1
The integrated USB v1.1 interface is a device-only controller. The interface supports
full-speed operation and 16 end points and includes an integrated transceiver. The
endpoints include:
• Six isochronous endpoints (three input and three output)
• Two control endpoints (one input and one output)
• Two interrupt endpoints (one input and one output)
• Six bulk endpoints (one input and one output)
For more information on the USB v1.1 interface, see Section 18.0, “Universal Serial Bus
(USB) v1.1 Device Controller” on page 468.
2.8 PCI
The IXP42X product line and IXC1100 control plane processors’ PCI controller is
compatible with the PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit
compatible bus and capable of operating as either a host or an option (i.e. not the
Host)
For more information on the PCI interface, see Section 6.0, “PCI Controller” on
page 208.
2.9 Memory Controller
The memory controller manages the interface to external SDRAM memory chips. The
interface:
• Operates at 133.32 MHz (which is 4 * OSC_IN input pin.)
• Supports eight open pages simultaneously
• Has two banks to support memory configurations from 8 Mbyte to 256 Mbyte