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Intel
®
IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
44 Order Number: 252480-006US
3.0 Intel XScale
®
Processor
This chapter provides functional descriptions of the Intel XScale
®
Processor.
3.1 Memory Management Unit
This section describes the memory management unit implemented in Intel
®
IXP42X
Product Line of Network Processors and IXC1100 Control Plane Processor.
The Intel XScale
®
Processor implements the Memory Management Unit (MMU)
Architecture specified in the ARM* Architecture Reference Manual. To accelerate
virtual-to-physical address translation, Intel XScale processor uses both an instruction
Translation Look-Aside Buffer (TLB) and a data TLB to cache the latest translations.
Each TLB holds 32 entries and is fully associative.
Not only do the TLBs contain the translated addresses, but also the access rights for
memory references.
If an instruction or data TLB miss occurs, a hardware translation-table-walking
mechanism is invoked to translate the virtual address to a physical address. Once
translated, the physical address is placed in the TLB along with the access rights and
attributes of the page or section. These translations can also be locked down in either
TLB to guarantee the performance of critical routines.
For more information, refer to “Exceptions” on page 47.
The Intel XScale processor allows system software to associate various attributes with
regions of memory:
• Cacheable
•Bufferable
• Line-allocate policy
• Write policy
•I/O
• Mini data cache
• Coalescing
For a description of page attributes, see “Cacheable (C), Bufferable (B), and eXtension
(X) Bits” on page 45. For information on where these attributes have been mapped in
the MMU descriptors, see “New Page Attributes” on page 152.
Note: The virtual address with which the TLBs are accessed may be remapped by the PID
register. For a description of the PID register, see “Register 13: Process ID” on page 84.
ARM MMU Version 5 Architecture introduces the support of tiny pages, which are
1 Kbyte in size. The reserved field in the first-level descriptor (encoding 0b11) is used
as the fine page table base address. The exact bit fields and the format of the first and
second-level descriptors can be found in “New Page Attributes” on page 152.