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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 269
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
6.14.2.18 AHB to PCI DMA PCI Address Register 0
(PCI_ATPDMA0_PCIADDR)
6.14.2.19 AHB to PCI DMA Length Register 0
(PCI_ATPDMA0_LENGTH)
Register Name: PCI_ATPDMA0_PCIADDR
Hex Offset Address: 0xC0000044 Reset Hex Value: 0x00000000
Register
Description:
Destination address on the PCI bus for AHB to PCI DMA transfers. Paired with pci_atpdma1_pciaddr to
allow buffering of DMA transfer requests.
Access: See below.
31 210
address 0 0
Register
PCI_ATPDMA0_PCIADDR
Bits Name Description
Reset
Value
PCI Access AHB Access
31:2 address PCI word address 0x00000000 RO RW
1:0 Lower PCI address bits hard-wired to zero. 00 RO RO
Register Name: PCI_ATPDMA0_LENGTH
Hex Offset Address: 0xC0000048 Reset Hex Value: 0x00000000
Register
Description:
Provides word count and control for AHB to PCI DMA transfers. Paired with pci_atpdma1_length to allow
buffering of DMA transfer requests.
Access: See below.
31 30 29 28 27 16 15 0
EN
(Rsvd)
DS
(Reserved) Wordcount
Register
PCI_ATPDMA0_LENGTH
Bits Name Description
Reset
Value
PCI Access AHB Access
31 EN
Channel enable. When set to a 1, executes a DMA
transfer if wordcount is nonzero. When 0, the channel
is disabled. Hardware clears this bit when the DMA
transfer is complete.
0RORW
30:2
9
(Reserved). Read as 0. 00 RO RO
28 DS
Data Swap indicator. When set to a 1, data from the
AHB bus is byte swapped before being sent to the PCI
bus. When 0, no swapping is done.
0RORW
27:1
6
(Reserved). Read as 0. 0x000 RO RO
15:0 wordcount Number of words to transfer. 0x0000 RO RW