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Intel
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IXP42X product line and IXC1100 control plane processors—Ethernet MAC A
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
420 Order Number: 252480-006US
15.1.4 Transmitting Ethernet Frames with MII Interfaces
Using IXP42X product line and IXC1100 control plane processors API calls, the Intel
XScale processor can request that packets be transmitted by the MII Interface. The
Intel XScale processor prepares an Ethernet packet to be transmitted. When the
preparation is complete, the Intel XScale processor uses the Intel-supplied API calls to
inform the Ethernet NPE that a packet is ready to be transmitted. The Ethernet NPE
fetches the packet from the SDRAM attached to the IXP42X product line and IXC1100
control plane processors and forwards the data over the NPE coprocessor interface to
the 256-byte Transmit FIFO contained in the Ethernet coprocessor.
Figure 82. MDIO Write
Notes:
1. ST (Start Bits) is a signal that is logic 0 followed by logic 1 after a PREAMBLE stage.
2. OC (Op Code) is a two-bit signal that informs the destination PHYs if the current requested transaction is a read or a
write. Logic0 followed by logic 1 indicates a write transaction is requested. Logic 1 followed by logic 0 indicates a read
transaction.
3. TA (Turn Around) is a two-bit, turn-around time used to allow the control of the MDIO to change directions. For write
operations, the TA bits will be logic 1 followed by logic 0. For read transactions, the TA bits will be high-impedance (Z)
followed by the selected PHY driving the MDIO signal with logic 0.
4. For write operations, the Management Interface Master will drive the MDIO signal for the duration of the access.
5. For read operation, the Management Interface Master will drive the MDIO signal until the turn around cycle. The PHY will
drive the MDIO signal for the second bit of the turn around and the remaining sixteen data bits.
Figure 83. MDIO Read
Notes:
1. ST (Start Bits) is a signal that is logic 0 followed by logic 1 — after a PREAMBLE stage.
2. OC (Op Code) is a two-bit signal that informs the destination PHYs, if the current requested transaction is a read or a
write. Logic 0 followed by logic 1 indicates a write transaction is requested. Logic 1 followed by logic 0 indicates a read
transaction.
3. TA (Turn Around) is a two-bit, turn-around time used to allow the control of the MDIO to change directions. For write
operations, the TA bits will be logic 1 followed by logic 0. For read transactions, the TA bits will be high-impedance (Z)
followed by the selected PHY driving the MDIO signal with logic 0.
4. For write operations, the Management Interface Master will drive the MDIO signal for the duration of the access.
5. For read operation, the Management Interface Master will drive the MDIO signal until the turn around cycle. The PHY will
drive the MDIO signal for the second bit of the turn around and the remaining sixteen data bits.
MDC
MDIO
PHY ADDR
(4:0)
REG ADDR
(4:0)
MDIOCMD2
(7:0)
MDIOCMD1
(7:0)
PREAMBLE
32 consecutive 1s
ST
OC
TA
4 3 2 1 0 4 3 2 1
151413121110 9 8 7 6 5 4 3 2 1 0
0
B2171-01
MDC
MDIO
PHY ADDR
(4:0)
REG ADDR
(4:0)
MDIOCMD2
(7:0)
MDIOCMD1
(7:0)
PREAMBLE
32 consecutive 1s
ST
OC
TA
4 3 2 1 0 4 3 2 1
151413121110 9 8 7 6 5 4 3 2 1 0
0
B2170-01