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Intel
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IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
300 Order Number: 252480-006US
• T2 – Setup/Chip Select Timing
• T3 – Strobe Timing
• T4 – Hold Timing
• T5 – Recovery Phase
The expansion-bus address is used to present the 24 bits of the address [23:0] used
for the expansion bus access accompanied by an address latch enable output signal,
EX_ALE. The address phase normally last one clock cycle, in non-multiplexed mode,
and two clock cycles, in multiplexed mode. The address phase may be extended by one
to three clock cycles using the T1 – Address Timing parameter, bits 29:28 in the Timing
and Control (EXP_TIMING_CS) Register for the particular Chip Select. When the
address phase T1 is extended, the ALE pulse is extended and always de-asserts one
cycle prior to the end of the T1 phase.
In multiplexed mode only, the EX_ALE signal is asserted with the address at the
beginning of the address phase and de-asserted one clock cycle later to provide plenty
of address setup time to an external device or latch. The address is placed onto the 16-
bit data bus — along with EX_ADDR [0:7] signals during the first cycle of the address
phase — when using the ALE signal. The lower 16 bits of address are placed on the
data bus and the upper bits of address are placed on the address bus signals EX_ADDR
[23:16]. The ALE is used to capture the address signals.
During the second cycle of the address phase, the data bus now will output data —
when attempting to complete a write — or tristate — when attempting to complete a
read. The address signals will retain their state.
Due to the fact that, in HPI mode of operation, it is possible to begin an access to a
busy device (EX_RDY is false), special consideration must be taken with programming
the T1 – Address Timing parameter when using the chip select in HPI mode. The T1 –
Address Timing parameter must be set to a minimum of two additional cycles (T1 must
equal to 0x2). Programming the T1 – Address Timing parameter to this value ensures
that the asynchronous EX_RDY input is sampled and available to the controlling
hardware logic before beginning the new HPI access over the expansion bus.
The chip-select signal is presented for one expansion bus phase before the Strobe
Phase. The chip select will be presented for the remainder of the expansion bus cycles
(setup, strobe, and hold phases).
The Setup/Chip Select Timing phase may also be extended by one to three clock cycles,
using bits 27:26 of the Timing and Control (EXP_TIMING_CS) Register, T2 – Setup/Chip
Select Timing parameter. In HPI mode of operation, T2 is defined as the time required
by the external DSP device to drive EX_RDY false for the current access plus the time
required by the Expansion Bus Controller to sample and synchronize the EX_RDY
signal. The T2 – Setup/Chip Select Timing parameter must have a minimum value of
two additional cycles (T2 must equal 0x2). Programming the T2 – Setup/Chip Select
Timing parameter to be three clock cycles in length ensures that when the Strobe
Phase, T3, begins, the Strobe Phase will be able to sample the EX_RDY signal and exit
the Strobe Phase at the proper time.
The Strobe Phase of an expansion-bus access is when the read or write strobe is
applied. The 24 Expansion Bus Interface Address bits are maintained in non-
multiplexed mode or the Expansion Bus Interface Data bus is switched from address to
data when configured in multiplexed mode during the Strobe Phase.
The Strobe Phase may be extended from one to 15 clock cycles, as defined by
programming bits 25:22 of the Timing and Control (EXP_TIMING_CS) Register, T3 –
Strobe Timing parameter. In HPI mode of operation, the T3 – Strobe Timing parameter
must have a minimum value of one additional cycle (T3 must equal 0x1). Programming