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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 19
—Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
86 T1 Transmit Frame................................................................................................. 448
87 T1 Receive Frame .................................................................................................. 448
88 E1 Transmit Frame................................................................................................. 449
89 E1 Receive Frame .................................................................................................. 450
90 MVIP, Interleaved Mapping of a T1 Frame to an E1 Frame ........................................... 452
91 MVIP, Frame Mapping a T1 Frame to an E1 Frame...................................................... 453
92 MVIP, Byte Interlacing Two E1 Streams Onto a 4.096-Mbps Backplane.......................... 453
93 MVIP, Byte Interleaving Two T1 Streams Onto a 4.096-Mbps Backplane ........................ 454
94 MVIP, Byte Interleaving Four E1 Streams on a 8.192-Mbps Backplane Bus..................... 455
95 MVIP, Byte Interleaving Four T1 Streams on a 8.192-Mbps Backplane Bus..................... 455
96 NRZI Bit Encoding Example ..................................................................................... 462
97 UTOPIA Level-2 Coprocessor ................................................................................... 530
98 UTOPIA Level-2 MPHY Transmit Polling ..................................................................... 532
99 UTOPIA Level-2 MPHY Receive Polling ....................................................................... 535
100 TAP Controller State Diagram .................................................................................. 539
101 AHB Queue Manager .............................................................................................. 547
Tables
1 Acronyms and Terminology ....................................................................................... 27
2 Network Processor Functions ..................................................................................... 38
3 Data Cache and Buffer Behavior When X = 0 ............................................................... 46
4 Data Cache and Buffer Behavior When X = 1 ............................................................... 47
5 Memory Operations that Impose a Fence..................................................................... 47
6 Valid MMU and Data/Mini-Data Cache Combinations ..................................................... 48
7 MRC/MCR Format..................................................................................................... 74
8 LDC/STC Format when Accessing CP14 ....................................................................... 75
9 CP15 Registers ........................................................................................................ 75
10 ID Register ............................................................................................................. 76
11 Cache Type Register................................................................................................. 77
12 ARM
*
Control Register .............................................................................................. 77
13 Auxiliary Control Register.......................................................................................... 79
14 Translation Table Base Register ................................................................................. 79
15 Domain Access Control Register................................................................................. 80
16 Fault Status Register ................................................................................................ 80
17 Fault Address Register .............................................................................................. 81
18 Cache Functions....................................................................................................... 81
19 TLB Functions.......................................................................................................... 82
20 Cache Lock-Down Functions ...................................................................................... 83
21 Data Cache Lock Register.......................................................................................... 83
22 TLB Lockdown Functions ........................................................................................... 83
23 Accessing Process ID................................................................................................ 84
24 Process ID Register .................................................................................................. 84
25 Accessing the Debug Registers................................................................................... 85
26 Coprocessor Access Register...................................................................................... 86
27 CP14 Registers ........................................................................................................ 86
28 Accessing the Performance Monitoring Registers .......................................................... 87
29 PWRMODE Register .................................................................................................. 87
30 Clock and Power Management ................................................................................... 88
31 CCLKCFG Register.................................................................................................... 88
32 Accessing the Debug Registers................................................................................... 88
33 Debug Control and Status Register (DCSR).................................................................. 90
34 Event Priority .......................................................................................................... 93
35 Instruction Breakpoint Address and Control Register (IBCRx)......................................... 96
36 Data Breakpoint Register (DBRx) ............................................................................... 96
37 Data Breakpoint Controls Register (DBCON) ................................................................ 97