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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 531
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
18.5.34 UDC Data Register 4 (UDDR4)
Endpoint 4 is a double-buffered, isochronous OUT endpoint that is 256 bytes deep. The
UDC generates an interrupt when the EOP is received.
Because it is double-buffered, up to two packets of data may be ready. The data can be
removed from the UDC via a direct read from the Intel XScale
®
processor. If one
packet is being removed and the packet behind it has already been received, the UDC
issues a NAK to the host the next time it sends an OUT packet to Endpoint 4.
This NAK condition remains in place until a full packet space is available in the UDC at
Endpoint 4.
18.5.35 UDC Data Register 5 (UDDR5)
Endpoint 5 is an interrupt IN endpoint that is 8 bytes deep. Data must be loaded via
direct Intel XScale
®
processor writes.
Because the USB system is a host-initiator model, the host must poll Endpoint 5 to
determine interrupt conditions. The UDC can not initiate the transaction.
Register Name: UDDR4
Hex Offset Address: 0 x C800B400 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 4 Data Register
Access: Read
Bits
31 87 0
(Reserved) (8-Bit Data)
X 00000000
Resets (Above)
Register
UDDR4
Bits Name Description
31:8 Reserved for future use.
7:0 DATA Top of endpoint data currently being read.
Register Name: UDDR5
Hex Offset Address: 0 x C800B008 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 5 Data Register
Access: Write.
Bits
31 87 0
(Reserved) (8-Bit Data)
X 00000000
Resets (Above)