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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
22 Order Number: 252480-006US
148 Processors’ with Ethernet Interface ...........................................................................436
149 Ethernet MAC B Registers ........................................................................................436
150 Processors with HSS ...............................................................................................438
151 HSS Tx/Rx Clock Output..........................................................................................445
152 HSS Tx/Rx Clock Output Frequencies and PPM Error....................................................446
153 HSS Tx/Rx Clock Output Frequencies And Their Associated Jitter Characterization ........... 446
154 HSS Frame Output Characterization ..........................................................................446
155 Jitter Definitions.....................................................................................................447
156 Endpoint Configuration: Universal Serial Bus Device Controller .....................................460
157 USB States ............................................................................................................461
158 Endpoint Field Addressing........................................................................................463
159 IN, OUT, and SETUP Token Packet Format .................................................................464
160 SOF Token Packet Format........................................................................................464
161 Data Packet Format ................................................................................................464
162 Handshake Packet Format .......................................................................................465
163 Bulk Transaction Formats ........................................................................................465
164 Isochronous Transaction Formats .............................................................................466
165 Control Transaction Formats ....................................................................................466
166 Interrupt Transaction Formats..................................................................................467
167 Host Device Request Summary.................................................................................468
168 USB-Device Register Descriptions .............................................................................470
169 Processors’ Devices with UTOPIA ..............................................................................528
170 JTAG Instruction Set ...............................................................................................543
171 JTAG Device Register Values ....................................................................................545
172 AHB Queue Manager Memory Map ............................................................................548
173 Queue Status Flags.................................................................................................551