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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
154 Order Number: 252480-006US
When setting multiple CP15 registers, system software may opt to delay the assurance
of their update. This is accomplished by executing CPWAIT only after the sequence of
MCR instructions.
The CPWAIT sequence guarantees that CP15 side-effects are complete by the time the
CPWAIT is complete. It is possible, however, that the CP15 side-effect will take place
before CPWAIT completes or is issued. Programmers should take care that this does
not affect the correctness of their code.
3.8.3.4 Event Architecture
3.8.3.4.1 Exception Summary
Table 72 shows all the exceptions that the Intel XScale processor may generate, and
the attributes of each. Subsequent sections give details on each exception.
Example 17. CPWAIT: Canonical Method to Wait for CP15 Update
;; The following macro should be used when software needs to be
;; assured that a CP15 update has taken effect.
;; It may only be used while in a privileged mode, because it
;; accesses CP15.
MACRO CPWAIT
MRC P15, 0, R0, C2, C0, 0 ; arbitrary read of CP15
MOV R0, R0 ; wait for it
SUB PC, PC, #4 ; branch to next instruction
; At this point, any previous CP15 writes are
; guaranteed to have taken effect.
ENDM
Table 72. Exception Summary (Sheet 1 of 2)
Exception Description Exception Type
1
Precise Updates FAR
Reset Reset N N
FIQ FIQ N N
IRQ IRQ N N
External Instruction Prefetch Y N
Instruction MMU Prefetch Y N
Instruction Cache Parity Prefetch Y N
Notes:
1. Exception types are those described in the ARM* Architecture Reference Manual.
2. Refer to “Software Debug” on page 88 for more details.