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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 421
Ethernet MAC A—Intel
®
IXP42X product line and IXC1100 control plane processors
Once the data has reached a predefined trigger point — known as the Buffer Size for
Transmit Register (TXBUFFSIZE), in the Transmit FIFO — or the End-of-Frame signal is
received, a data packet will begin to be transmitted over the MII interface. The Buffer
Size for Transmit Register (TXBUFFSIZE), for each frame transmitted, holds the
minimum number of bytes that must be contained in the transmit FIFO before the
frames transmission may start. If the total size of the frame is less than the Buffer Size
for Transmit Register, the frame will be transmitted when the end of frame signal is
received.
When entries leave the bottom of the Transmit FIFO, the entries are 32-bits. Setting of
the Buffer Size for Transmit Register (TXBUFFSIZE), the Threshold for Partially Full
(THRESHPF), and the Threshold for Partially Empty (THRESHPE) are tightly coupled
with the code written for the NPE core. Manipulation of the values will result in
unpredictable behavior.
The Threshold for Partially Full (THRESHPF) is a parameter that — when the number of
entries in the Transmit or Receive FIFOs is larger than the value programmed in this
register — a status flag, going to the NPE core, will be set. The Threshold for Partially
Full (THRESHPE) is a parameter that — when the number of entries in the Transmit or
Receive FIFOs is smaller than the value programmed in this register — a status flag,
going to the NPE core, will be set.
After the data begins leaving the FIFO, the data is sent through a converter function
that is used to convert the bits from 32-bits to byte-wide entries to supply to the
Transmit Engine. The Transmit Engine will take the bytes supplied from the converter,
manipulate the data as defined by MAC control registers and forward the data over the
MII interface as 4-bit nibbles.
The Transmit Engine can be configured using IXP42X product line and IXC1100 control
plane processors’ API calls to:
• Append a Frame Check Sequence to the end of a transmitted frame
• Autonomously append bytes to frames that are smaller than the minimum frame
size (64 bytes)
• Enable/Disable transmit retries
• Set the number of times a frame can be retried due to collision conditions before
being dropped
• Select half- or full-duplex mode of operation
• Select a one- or two-part deferral to be used
• Enable/Disable the Transmit Engine
A Frame Check Sequence (FCS) can be autonomously generated and appended to the
end of each Ethernet frame. The Frame Check Sequence can be used to ensure proper
delivery of data between two Ethernet devices. The Frame Check Sequence consists of
a 4-byte Cyclic Redundancy Generator that adheres to the polynomial:
The Frame Check Sequence will be computed over all fields beginning after the Start-
of-Frame Delimiter (SFD) and up to the Frame Check Sequence (FCS) value.
Autonomous insertion of the Frame-Check Sequence into the transmitted frame can be
enabled/disabled by setting bit 4 of Transmit Control Register 1 (TXCTRL1). Setting bit
4 of Transmit Control Register 1 (TXCTRL1) to logic 1 will cause a CRC value to be
generated and inserted into the Frame-Check Sequence field of the transmitted frame.
Setting bit 4 of Transmit Control Register 1 (TXCTRL1) to logic 0 will cause a
transmitted frame to be sent without a Frame Check Sequence attached.
G(x) = x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x
4 +x 2 +x +1