Filter
Top Products
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 163
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
3.9.4.4 Multiply Instruction Timings
CMN1122
CMP1122
EOR1122
MOV1122
MVN1122
ORR1122
RSB1122
RSC1122
SBC1122
SUB1122
TEQ1122
TST1122
Table 81. Multiply Instruction Timings (Sheet 1 of 2)
Mnemonic
Rs Value
(Early
Termination)
S-Bit
Valu
e
Minimum
Issue
Latency
Minimum Result
Latency
*
Minimum Resource
Latency (Throughput)
MLA
Rs[31:15] =
0x00000
or
Rs[31:15] = 0x1FFFF
01 2 1
12 2 2
Rs[31:27] = 0x00
or
Rs[31:27] = 0x1F
01 3 2
13 3 3
all others
01 4 3
14 4 4
MUL
Rs[31:15] =
0x00000
or
Rs[31:15] = 0x1FFFF
01 2 1
12 2 2
Rs[31:27] = 0x00
or
Rs[31:27] = 0x1F
01 3 2
13 3 3
all others
01 4 3
14 4 4
Note: If the next instruction needs to use the result of the multiply for a shift by immediate or as Rn in a
QDADD or QDSUB, one extra cycle of result latency is added to the number listed.
Table 80. Data Processing Instruction Timings (Sheet 2 of 2)
Mnemonic
<shifter operand> is NOT a Shift/
Rotate by Register
<shifter operand> is a Shift/Rotate
by Register OR
<shifter operand> is RRX
Minimum Issue
Latency
Minimum Result
Latency
*
Minimum Issue
Latency
Minimum Result
Latency
*
Note: If the next instruction needs to use the result of the data processing for a shift by immediate or as Rn
in a QDADD or QDSUB, one extra cycle of result latency is added to the number listed.