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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 77
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
3.5.1.2 Register 1: Control and Auxiliary Control Registers
Register 1 is made up of two registers, one that is compliant with ARM Version 5TE and
referred by opcode_2 = 0x0, and the other which is specific to the Intel XScale
processor is referred by opcode_2 = 0x1. The latter is known as the Auxiliary Control
Register.
The Exception Vector Relocation bit (bit 13 of the ARM control register) allows the
vectors to be mapped into high memory rather than their default location at address 0.
This bit is readable and writable by software. If the MMU is enabled, the exception
vectors will be accessed via the usual translation method involving the PID register
(see “Register 13: Process ID” on page 84) and the TLBs. To avoid automatic
application of the PID to exception vector accesses, software may relocate the
exceptions to high memory.
Table 11. Cache Type Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00001011000 Dsize 101010000 Isize 101010
reset value: As Shown
Bits Access Description
31:29 Read-as-Zero / Write Ignored Reserved
28:25 Read / Write Ignored
Cache class = 0b0101
The caches support locking, write back and round-robin
replacement. They do not support address by index.
24 Read / Write Ignored Harvard Cache
23:21 Read-as-Zero / Write Ignored Reserved
20:18 Read / Write Ignored
Data Cache Size (Dsize)
0b110 = 32 KB
17:15 Read / Write Ignored Data cache associativity = 0b101 = 32-way
14 Read-as-Zero / Write Ignored Reserved
13:12 Read / Write Ignored Data cache line length = 0b10 = 8 words/line
11:9 Read-as-Zero / Write Ignored Reserved
8:6 Read / Write Ignored
Instruction cache size (Isize)
0b110 = 32 KB
5:3 Read / Write Ignored Instruction cache associativity = 0b101 = 32-way
2 Read-as-Zero / Write Ignored Reserved
1:0 Read / Write Ignored Instruction cache line length = 0b10 = 8 words/line
Table 12. ARM
*
Control Register (Sheet 1 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VIZ0RSB1111CAM
reset value: writeable bits set to 0
Bits Access Description
31:14
Read-Unpredictable /
Write-as-Zero
Reserved
13 Read / Write
Exception Vector Relocation (V).
0 = Base address of exception vectors is 0x0000,0000
1 = Base address of exception vectors is 0xFFFF,0000
12 Read / Write
Instruction Cache Enable/Disable (I)
0 = Disabled
1 = Enabled