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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 343
Universal Asynchronous Receiver Transceiver (UART)—Intel
®
IXP42X product line and IXC1100
control plane processors
The error flags position will remain constant, independent of the character size. The
mode of operation and FIFO control parameters will be programmed using the FIFO
Control Register (FCR).
The FIFO Control Register is an 8-bit register that configures the UARTs’ mode of
operation. The Transmit and Receive FIFO Enable Bit (TRFIFOE) — Bit 0 of the FIFO
Control Register — determines the UARTs’ mode of operation: FIFO Mode or Non-FIFO
Mode. When set to logic 0, the UART will function in Non-FIFO Mode. When set to logic
1, the UART will function in FIFO Mode.
Two bits of the FIFO Control Register are used to reset the Transmit and Receive FIFO:
the Reset Transmit FIFO bit (bit 2 of FCR) and the Reset Receive FIFO (bit 1 of FCR).
Writing logic 0 to these bits has no effect. Writing logic 1 to the Reset Transmit FIFO bit
will cause the Transmit FIFO counter to be reset to 0 and the transmit-data request bit
to be set in the Line-Status Register.
Writing logic 1 to the Reset Receive FIFO bit will cause the Receive FIFO counter to be
reset to 0 and the data ready bit in the Line-Status Register to be cleared. The Overrun
Error Flag, Parity Error Flag, Framing Error Flag, and Break Interrupt Flag in the Line
Status Register will remain unaltered. The Reset Transmit FIFO and Reset Receive FIFO
will be cleared autonomously when the reset has been completed.
The Receive FIFO interrupt trigger level also is set in the FIFO Control Register. The
Receive FIFO interrupt trigger level is used to generate an interrupt when the number
of characters in the Receive FIFO is greater than to or equal to the trigger-level value.
The Interrupt Trigger Level is defined as bit 6 and bit 7 of the FIFO Control Register. The
bit definitions are shown in Table 133.
The UART must be configured prior to transmitting and receiving data to and from the
UART. The Transmit Holding Register (THR) is used to transmit characters over the
UART interface. The Receive Buffer Register is used to receive characters from the
UART interface.
Transmitting UART data can be implemented using FIFO Mode or Non-FIFO mode. In
FIFO mode, writing a character to the Transmit Holding Register will put data on the top
of the transmit FIFO. In Non-FIFO mode, writing a character to the Transmit Holding
Register will put data in the Transmit Holding Register. The next character transmitted
will be the character contained in the Transmit Holding Register.
If characters less than 8 bits are sent, the characters will need to be right-justified. For
example, if a 5-bit data character is to be transmitted with a binary value of 01011. The
data written to the Transmit Holding Register will need to be written as hexadecimal
0x0B.
Receiving UART data can be implemented using FIFO Mode or Non-FIFO mode. In FIFO
mode, reading a character from the Receive Buffer Register will read a character from
the bottom of the receive FIFO. In Non-FIFO mode, reading a character from the
Receive Buffer Register will read the data contained in the Receive Buffer Register. The
next character received will be the character contained in the Receive Buffer Register.
Table 133. UART FIFO Trigger Level
Interrupt Trigger Level [7:6] Description
00 1 byte or more in the FIFO causes an interrupt
01 8 bytes or more in the FIFO causes an interrupt
10 16 bytes or more in the FIFO causes an interrupt
11 32 bytes or more in the FIFO causes an interrupt