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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 485
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
18.5.3 UDC Endpoint 1 Control/Status Register (UDCCS1)
The UDC Endpoint 1control status register contains 6 bits that are used to operate
endpoint 1, a Bulk IN endpoint.
18.5.3.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is active if one or fewer data packets remain in the
transmit FIFO. TFS is cleared when two complete packets of data remain in the FIFO. A
complete packet of data is signified by loading 64 bytes of data or by setting
UDCCS1[TSP].
Register Name: UDCCS0
Hex Offset Address: 0 x C800B010 Reset Hex Value:
0 x 00000000
Register
Description:
Universal Serial Bus Device Controller Endpoint 0 Control and Status Register
Access: Read/Write
Bits
31 876543210
(Reserved)
SA
RNE
FST
SST
DRWF
FTF
IPR
OPR
X 00000000
Resets (Above)
Register
UDCCS0
Bits Name Description
31:8 Reserved for future use
7SA
Setup Active (read/write 1 to clear)
1 = Setup command is active on the USB
6RNE
Receive FIFO not empty (read-only).
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
5FST
Force stall (read/write 1 to set).
1 = Force stall handshake
4 SST
Sent stall (read/write 1 to clear).
1 = UDC sent stall handshake
3DRWF
Device remote wake-up feature (read-only)
0 = Device Remote Wake-Up Feature is disabled.
1 = Device Remote Wake-Up Feature is enabled.
2FTF
Flush Tx FIFO (always read 0/write 1 to set)
1 = Flush the contents of Tx FIFO.
1IPR
IN packet ready (always read 0/write 1 to set).
1 = IN packet ready.
0OPR
OUT packet ready (read/write 1 to clear)
1 = OUT packet ready.