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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 235
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
For each direction, when a DMA channel is executing one transfer using the active DMA
register set, the other DMA register set can be set-up by the Intel XScale processor to
specify the next transfer. Both DMA channels can run concurrently so that individual
PCI-to-AHB transfers and AHB-to-PCI transfers that make up the DMA transfers are
interleaved on the AHB and PCI bus.
Individual DMA-complete and DMA-error status indication is provided for each channel
using the DMA Control Register (PCI_DMACTRL) with an interrupt that may be
optionally generated in each case.
The register sets associated with the DMA channels are as follows:
1. PCI to AHB Transfers
a. Register Set 0
— PCI to AHB DMA AHB Address Register 0 (PCI_PTADMA0_AHBADDR)
— PCI to AHB DMA PCI Address Register 0 (PCI_PTADMA0_PCIADDR)
— PCI to AHB DMA Length Register 0 (PCI_PTADMA0_LENGTH)
b. Register Set 1
— PCI to AHB DMA AHB Address Register 1 (PCI_PTADMA1_AHBADDR)
— PCI to AHB DMA PCI Address Register 1 (PCI_PTADMA1_PCIADDR)
— PCI to AHB DMA Length Register 1 (PCI_PTADMA1_LENGTH)
2. AHB to PCI Transfers
a. Register Set 0
— AHB to PCI DMA AHB Address Register 0 (PCI_ATPDMA0_AHBADDR)
— AHB to PCI DMA PCI Address Register 0 (PCI_ATPDMA0_PCIADDR)
— AHB to PCI DMA Length Register 0 (PCI_ATPDMA0_LENGTH)
b. Register Set 1
— AHB to PCI DMA AHB Address Register 1 (PCI_ATPDMA1_AHBADDR)
— AHB to PCI DMA PCI Address Register 1 (PCI_ATPDMA1_PCIADDR)
— AHB to PCI DMA Length Register 1 (PCI_ATPDMA1_LENGTH)
The PCI Address Registers described above are used to specify the beginning 32-bit
word address for the PCI side of the DMA transfers. The AHB Address Registers,
described above, are used to specify the beginning 32-bit word address for the AHB
side of the DMA transfers. The least significant two bits of both addresses are hard-
wired to logic 0. Thus, all transfers are word-aligned.
The Length Registers are used for three purposes:
• Sixteen bits to define a word count
Bits 15:0 of the Length Registers define the word count.
• One bit to enable the DMA transfer
Bit 31 of the Length Registers enables the DMA transfer to execute. When bit 31 of
the Length Registers is set to logic 1, the DMA transfer executes until a word count
of zero is reached. When the word count reaches zero and bit 31 of the Length
Registers is set to logic 1, bit 31 of the Length Register is cleared to logic 0. When
bit 31 of the Length Register is set to logic 0, the register set associated with the
DMA channel is disabled. The second register set may be active and using the DMA
channel when the first DMA has finished.
• One bit to define the byte order of the data transferred.