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Intel
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IXP42X product line and IXC1100 control plane processors—Interrupt Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
400 Order Number: 252480-006US
For instance, interrupt number 0 is disabled and an interrupt occurs on interrupt
number 0. The interrupt generated by interrupt number 0 will not be seen by the Intel
XScale processor.
The Interrupt-Enable Register is a 32-bit register that can individually enable or disable
each of the 32 interrupts. Bit 0 of the Interrupt-Enable Register corresponds to
interrupt number 0 (WAN/Voice NPE). Bit 31 of the Interrupt-Enable Register
corresponds to interrupt number 31 (Software Interrupt 1).
Logic 1 written to a bit in the Interrupt-Enable Register will enable the corresponding
interrupt number. Writing logic 0 to the same bit in the Interrupt-Enable Register will
disable the corresponding interrupt number.
For example, the Interrupt-Enable Register is written with a hexadecimal value of
0x0000000A. The result of this write would enable interrupt number 1 (Ethernet NPE A)
and interrupt number 3 (Queue Manager Queues 1-32). All other interrupt numbers
would be disabled. All interrupts are disabled upon receiving a reset.
13.4 Reading Interrupt Status
The IXP42X product line and IXC1100 control plane processors provide several
mechanisms in which interrupt status can be obtained from the Interrupt Controller.
One method of obtaining interrupt status is to read the interrupt status register directly
(INTR_ST).
The Interrupt Status Register is a 32-bit register that has a one-for-one relationship
with the interrupt number. Interrupt number 0 (WAN/Voice NPE) will be the status
represented on bit 0 of the Interrupt Status Register and interrupt number 31 will be
the status represented on bit 31 of the Interrupt Status Register.
Reading Logic 1 from a bit in the Interrupt Status Register represent that the device
connected to that particular interrupt number has asserted an interrupt to the Interrupt
Controller. For example, a read is performed on the Interrupt Status Register and the
result returned is a hexadecimal 0x00000002. The Interrupt Status Register is telling
the Intel XScale processor that the interrupt number 1 (Ethernet NPE A) has caused an
interrupt.
The Intel XScale processor will service the interrupt and clear the interrupt by updating
the register that caused the interrupt condition in the Ethernet NPE A. Using the
Interrupt Status Register allows an interrupt service routine to assign relative priorities
to the interrupts and removes all relationship from the priority algorithms or the
interrupt types assigned by the IXP42X product line and IXC1100 control plane
processors Interrupt Controller. The Interrupt Status Register is set to all zeros upon
reset.
All other methods of reading interrupt status will involve the use of the register sets
provided by the IXP42X product line and IXC1100 control plane processors to aid in the
determination of which interrupts should be serviced first.
The IXP42X product line and IXC1100 control plane processors provide the capability of
reading the interrupt status of the interrupt numbers that have been assigned as FIQ
interrupts or reading the interrupt status of the interrupt numbers that have been
assigned as IRQ interrupts. The status of the interrupt numbers — that have been
assigned as FIQ interrupts — can be read by reading the FIQ status register
(INTR_FIQ_ST). The status of the interrupt numbers that have been assigned as IRQ
interrupts can be read by reading the IRQ status register (INTR_IRQ_ST).