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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 41
Overview of Product Line—Intel
®
IXP42X product line and IXC1100 control plane processors
The memory controller only supports 32-bit memory. If a x16 memory chip is used, a
minimum of two memory chips would be required to facilitate the 32-bit interface
required by the IXP42X product line and IXC1100 control plane processors. A maximum
of four SDRAM memory chips may be attached to the processors.
The memory controller internally interfaces to the North AHB and South AHB with
independent peripherals. This architecture allows SDRAM transfers to be interleaved
and pipelined to achieve maximum possible efficiency. The maximum burst size
supported to the SDRAM Interface is 8-32 bit words. This burst size allows the best
efficiency/fairness performance between accesses from the North and South AHB.
For more information on the memory controller, see Section 7.0, “SDRAM Controller”
on page 276.
2.10 Expansion Bus
The expansion interface allows easy and — in most cases — glue-less connection to
peripheral devices. It also provides input information for device configuration after
reset. Some of the peripheral device types are flash, ATM control interfaces, and DSPs
used for voice applications. (Some voice configurations can be supported by the HSS
interfaces and the Intel XScale
®
Processor, implementing voice-compression
algorithms.)
The expansion bus interface is a 16-bit interface that allows an address range of
512 bytes to 16 Mbytes, using 24 address lines for each of the eight independent chip
selects.
Accesses to the expansion bus interface consists of five phases. Each of the five phases
can be lengthened or shortened by setting various configuration registers on a per-
chip-select basis. This feature allows the IXP42X product line and IXC1100 control
plane processors to connect to a wide variety of peripheral devices with varying speeds.
The expansion bus interface supports Intel or Motorola* microprocessor-style bus
cycles. The bus cycles can be configured to be multiplexed address/data cycles or
separate address/data cycles for each of the eight chip-selects.
Additionally, Chip Selects 4 through 7 can be configured to support Texas Instruments
HPI-8 or HPI-16 style accesses for DSPs.
The expansion bus interface is an asynchronous interface to externally connected
chips. However, a clock must be supplied to the IXP42X product line and IXC1100
control plane processors’ expansion bus interface for the interface to operate. This
clock can be driven from GPIO 15 or an external source. The maximum clock rate that
the expansion bus interface can accept is 66.66 MHz.
At the de-assertion of reset, the 24-bit address bus is used to capture configuration
information from the levels that are applied to the pins at this time. External pull-up/
pull-down resistors are used to tie the signals to particular logic levels
For more information on the Expansion Interface, see Section 8.0, “Expansion Bus
Controller” on page 292.
2.11 High-Speed Serial Interfaces
The High-Speed Serial interfaces are a six-signal interface that supports serial transfer
speeds from 512 KHz to 8.192 MHz.
For more information on the High-Speed Serial Interfaces, see Section 17.0, “High-
Speed Serial Interfaces” on page 448.