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Intel
®
IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
228 Order Number: 252480-006US
6.6.4 Initiated Type-1 Read Transaction
The following transaction is a PCI Configuration Read Cycle initiated from the IXP42X
product line and IXC1100 control plane processors. This diagram is to understand the
inner workings of PCI transfers and may not reflect actual operation of the PCI
Controller implemented on the IXP42X product line and IXC1100 control plane
processors. The transaction is initiated to PCI bus segment 0, Device number 0,
Function 0, and Base Address Register 0.
This configuration cycle is a Type 1 configuration cycle and is intended for another PCI
bus segment. Binary 01 being located in bits 1:0 of the PCI_AD bus during the address
phase denotes a Type 1 PCI Configuration cycle.
A hexadecimal value of 0xA — written on the PCI_C/BE_N bus during the address
phase — signifies that this is a PCI Bus Configuration Read Cycle. Due to the fact that
the access is on another PCI Bus Segment, the PCI_TRDY_N signal may take longer to
respond and therefore may be extended by several clocks and is not shown here.
Figure 36. Initiated PCI Type-0 Configuration Write Cycle
PCI_CLK
PCI_FRAME_N
PCI_AD (31:0)
PCI_IDSEL
PCI_C/BE_N
PCI_IRDY_N
PCI_TRDY_N
PCI_DEVSEL_N
0x00000110 DATA
0xB 0x0
INT_REQ_N
INT_GNT_N
Figure 37. Initiated PCI Type-1 Configuration Read Cycle
PCI_CLK
PCI_FRAME_N
PCI_AD (31:0)
PCI_IDSEL
PCI_C/BE_N
PCI_IRDY_N
PCI_TRDY_N
PCI_DEVSEL_N
0x00000011
DATA
0xA 0x0
INT_REQ_N
INT_GNT_N