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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Intel
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IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
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Another possibility is for a more complete debug handler is downloaded during reset.
The debug handler may support some operations, such as read memory, write memory,
etc. However, other operations, such as reading or writing a group of CP register, can
be downloaded dynamically. This method could be used to dynamically download
infrequently used debug handler functions, while the more common operations remain
static in the mini-instruction cache.
The Intel Debug Handler is a complete debug handler that implements the more
commonly used functions, and allows less frequently used functions to be dynamically
downloaded.
3.6.14.6 Mini-Instruction Cache Overview
The mini instruction cache is a smaller version of the main instruction cache. (For more
details on the main instruction cache, see “Instruction Cache” on page 52.) It is a
2-Kbyte, two-way set associative cache. There are 32 sets, each containing two ways
with each way containing eight words. The cache uses the round-robin replacement
policy.
The mini instruction cache is virtually addressed and addresses may be remapped by
the PID. However, since the debug handler executes in Special Debug State, address
translation and PID remapping are turned off. For application code, accesses to the mini
instruction cache use the normal address translation and PID mechanisms.
Normal application code is never cached in the mini instruction cache on an instruction
fetch. The only way to get code into the mini instruction cache is through the JTAG
LDIC function. Code downloaded into the mini instruction cache is essentially locked - it
cannot be overwritten by application code running on the IXP42X product line and
IXC1100 control plane processors. However, it is not locked against code downloaded
through the JTAG LDIC functions.
Application code can invalidate a line in the mini instruction cache using a CP15
Invalidate IC line function to an address that hits in the mini instruction cache.
However, a CP15 global invalidate IC function does not affect the mini instruction
cache.
The mini instruction cache can be globally invalidated through JTAG by the LDIC
Invalidate IC function or by a processor reset when the processor is not in HALT or LDIC
mode. A single line in the mini instruction cache can be invalidated through JTAG by the
LDIC Invalidate IC-line function.
3.6.15 Halt Mode Software Protocol
This section describes the overall debug process in Halt Mode. It describes how to start
and end a debug session and details for implementing a debug handler. Intel provides a
standard Debug Handler that implements some of the techniques in this section. The
Intel Debug Handler itself is a a document describing additional handler
implementation techniques and requirements.
3.6.15.1 Starting a Debug Session
Prior to starting a debug session in Halt Mode, the debugger must download code into
the instruction cache during reset, via JTAG. (“Downloading Code in ICache” on
page 116). This downloaded code should consist of:
• A debug handler
• An override default vector table
• An override relocated vector table (if necessary)