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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 17
—Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
21.3 Functional Description...................................................................................... 557
21.4 AHB Interface ................................................................................................. 558
21.4.1 Queue Control ..................................................................................... 559
21.4.2 Queue Status....................................................................................... 560
21.4.2.1 Status Update ........................................................................ 560
21.4.2.2 Flag Bus ................................................................................ 561
21.4.2.3 Status Interrupts .................................................................... 562
21.5 Register Descriptions ....................................................................................... 562
21.5.1 Queue Access Word Registers 0 - 63....................................................... 562
21.5.2 Queues 0-31 Status Register 0 - 3.......................................................... 563
21.5.3 Underflow/Overflow Status Register 0 - 1 ................................................ 563
21.5.4 Queues 32-63 Nearly Empty Status Register............................................ 564
21.5.5 Queues 32-63 Full Status Register.......................................................... 564
21.5.6 Interrupt 0 Status Flag Source Select Register 0 – 3 ................................. 565
21.5.7 Queue Interrupt Enable Register 0 – 1 .................................................... 566
21.5.8 Queue Interrupt Register 0 – 1 .............................................................. 566
21.5.9 Queue Configuration Words 0 - 63.......................................................... 566
Figures
1Intel
®
IXP425 Network Processor Block Diagram.......................................................... 31
2Intel
®
IXP423 Network Processor Block Diagram.......................................................... 32
3Intel
®
IXP422 Network Processor Block Diagram.......................................................... 33
4Intel
®
IXP421 Network Processor Block Diagram.......................................................... 34
5Intel
®
IXP420 Network Processor and Intel
®
IXC1100 Control Plane Processor
Block Diagram ......................................................................................................... 35
6Intel XScale
®
Technology Architecture Features ........................................................... 36
7 Example of Locked Entries in TLB ............................................................................... 52
8 Instruction Cache Organization .................................................................................. 53
9 Locked Line Effect on Round-Robin Replacement .......................................................... 57
10 BTB Entry ............................................................................................................... 59
11 Branch History......................................................................................................... 59
12 Data Cache Organization........................................................................................... 61
13 Mini-Data Cache Organization.................................................................................... 62
14 Locked Line Effect on Round-Robin Replacement .......................................................... 72
15 SELDCSR Hardware................................................................................................ 103
16 SELDCSR Data Register .......................................................................................... 104
17 DBGTX Hardware ................................................................................................... 105
18 DBGRX Hardware................................................................................................... 106
19 Rx Write Logic ....................................................................................................... 107
20 DBGRX Data Register ............................................................................................. 108
21 Message Byte Formats............................................................................................ 111
22 Indirect Branch Entry Address Byte Organization........................................................ 114
23 High Level View of Trace Buffer................................................................................ 114
24 LDIC JTAG Data Register Hardware .......................................................................... 117
25 Format of LDIC Cache Functions .............................................................................. 119
26 Code Download During a Cold Reset For Debug.......................................................... 120
27 Code Download During a Warm Reset For Debug........................................................ 122
28 Downloading Code in IC During Program Execution..................................................... 123
29 Processors’ RISC Super-Pipeline............................................................................... 169
30 Processors’ PCI Bus Configured as a Host .................................................................. 209
31 Processors’ PCI Bus Configured as an Option ............................................................. 209
32 Processors’ PCI Controller Block Diagram .................................................................. 210
33 Type 0 Configuration Address Phase ......................................................................... 214
34 Type 1 Configuration Address Phase ......................................................................... 215