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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 95
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
• Instruction breakpoint
• BKPT instruction
The processor ignores vector traps during monitor mode.
When an exception occurs in monitor mode, the processor takes the following actions:
• Disables the trace buffer
• Sets DCSR.moe encoding
• Sets FSR[9]
• R14_abt = PC of the next instruction to execute + 4 (for Data Aborts)
R14_abt = PC of the faulting instruction + 4 (for Prefetch Aborts)
•SPSR_abt = CPSR
• CPSR[4:0] = 0b10111 (ABORT mode)
•CPSR[5] = 0
• CPSR[6] = unchanged
•CPSR[7] = 1
• PC = 0xc (for Prefetch Aborts),
PC = 0x10 (for Data Aborts)
During abort mode, external debug breaks and trace buffer full breaks are internally
pended. When the processor exits abort mode, either through a CPSR restore or a write
directly to the CPSR, the pended debug breaks will immediately generate a debug
exception. Any pending debug breaks are cleared out when any type of debug
exception occurs.
When exiting, the debug handler should do a CPSR restore operation that branches to
the next instruction to be executed in the program under debug.
3.6.6 HW Breakpoint Resources
IXP42X product line and IXC1100 control plane processors’ debug architecture defines
two instruction and two data breakpoint registers, denoted IBCR0, IBCR1, DBR0, and
DBR1.
The instruction and data address breakpoint registers are 32-bit registers. The
instruction breakpoint causes a break before execution of the target instruction. The
data breakpoint causes a break after the memory access has been issued.
In this section Modified Virtual Address (MVA) refers to the virtual address ORed with
the PID. Refer to “Register 13: Process ID” on page 84 for more details on the PID. The
processor does not OR the PID with the specified breakpoint address prior to doing
address comparison. This must be done by the programmer and written to the
breakpoint register as the MVA. This applies to data and instruction breakpoints.
3.6.6.1 Instruction Breakpoints
The Debug architecture defines two instruction breakpoint registers (IBCR0 and
IBCR1). The format of these registers is shown in Table 35., Instruction Breakpoint
Address and Control Register (IBCRx). In ARM mode, the upper 30 bits contain a word
aligned MVA to break on. In Thumb mode, the upper 31 bits contain a half-word aligned
MVA to break on. In both modes, bit 0 enables and disables that instruction breakpoint
register. Enabling instruction breakpoints while debug is globally disabled (DCSR.GE=0)
may result in unpredictable behavior.