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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
4 Order Number: 252480-006US
3.4 Data Cache.......................................................................................................60
3.4.1 Data Cache Overview ..............................................................................60
3.4.2 Cacheability ...........................................................................................63
3.4.3 Reconfiguring the Data Cache as Data RAM ................................................68
3.5 Configuration ....................................................................................................73
3.5.1 CP15 Registers.......................................................................................75
3.5.1.1 Register 0: ID and Cache Type Registers ......................................76
3.5.1.2 Register 1: Control and Auxiliary Control Registers ........................77
3.5.1.3 Register 2: Translation Table Base Register ..................................79
3.5.1.4 Register 3: Domain Access Control Register..................................80
3.5.1.5 Register 4: Reserved .................................................................80
3.5.1.6 Register 5: Fault Status Register .................................................80
3.5.1.7 Register 6: Fault Address Register ...............................................81
3.5.1.8 Register 7: Cache Functions........................................................81
3.5.1.9 Register 8: TLB Operations.........................................................82
3.5.1.10 Register 9: Cache Lock Down......................................................82
3.5.1.11 Register 10: TLB Lock Down .......................................................83
3.5.1.12 Register 11-12: Reserved...........................................................84
3.5.1.13 Register 13: Process ID..............................................................84
3.5.1.14 The PID Register Affect On Addresses ..........................................84
3.5.1.15 Register 14: Breakpoint Registers................................................85
3.5.1.16 Register 15: Coprocessor Access Register.....................................85
3.5.2 CP14 Registers.......................................................................................86
3.5.2.1 Performance Monitoring Registers................................................87
3.5.2.2 Clock and Power Management Registers.......................................87
3.5.2.3 Software Debug Registers ..........................................................88
3.6 Software Debug.................................................................................................88
3.6.1 Definitions .............................................................................................89
3.6.2 Debug Registers .....................................................................................89
3.6.3 Debug Modes .........................................................................................89
3.6.3.1 Halt Mode ................................................................................90
3.6.3.2 Monitor Mode............................................................................90
3.6.4 Debug Control and Status Register (DCSR) ................................................90
3.6.4.1 Global Enable Bit (GE) ...............................................................91
3.6.4.2 Halt Mode Bit (H) ......................................................................91
3.6.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR) ......................................92
3.6.4.4 Sticky Abort Bit (SA)..................................................................92
3.6.4.5 Method of Entry Bits (MOE) ........................................................92
3.6.4.6 Trace Buffer Mode Bit (M)...........................................................92
3.6.4.7 Trace Buffer Enable Bit (E) .........................................................92
3.6.5 Debug Exceptions ...................................................................................92
3.6.5.1 Halt Mode ................................................................................93
3.6.5.2 Monitor Mode............................................................................94
3.6.6 HW Breakpoint Resources ........................................................................95
3.6.6.1 Instruction Breakpoints ..............................................................95
3.6.6.2 Data Breakpoints ......................................................................96
3.6.7 Software Breakpoints ..............................................................................98
3.6.8 Transmit/Receive Control Register ............................................................98
3.6.8.1 RX Register Ready Bit (RR).........................................................99
3.6.8.2 Overflow Flag (OV)..................................................................100
3.6.8.3 Download Flag (D)...................................................................100
3.6.8.4 TX Register Ready Bit (TR) .......................................................100
3.6.8.5 Conditional Execution Using TXRXCTRL.......................................101
3.6.9 Transmit Register .................................................................................101
3.6.10 Receive Register...................................................................................102
3.6.11 Debug JTAG Access...............................................................................102
3.6.11.1 SELDCSR JTAG Command ........................................................102