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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 341
Universal Asynchronous Receiver Transceiver (UART)—Intel
®
IXP42X product line and IXC1100
control plane processors
For example, the maximum time between a received character and a Receive Character
Time-Out Interrupt is 160 ms at 1,200 baud with a 12-bit receive character (i.e., 1
start, 8 data, 1 parity, and 2 stop bits).
The time-out interrupt is cleared by the IXP42X product line and IXC1100 control plane
processors reading the Receive FIFO or setting the RESETRF bit to logic 1, in the FIFO
Control Register.
If a Receive Character Time-Out Interrupt is active, the interrupt-time-out counter will
be reset only after the IXP42X product line and IXC1100 control plane processors reads
a character from the Receive FIFO. If a Receive Character Time-Out Interrupt is non-
active, the interrupt time-out counter will be reset after the IXP42X product line and
IXC1100 control plane processors reads a character from the Receive FIFO or when a
new character is placed into the Receive FIFO by the receive interface.
The Transmit Data Request Interrupt Enable can be used in Non-FIFO mode or FIFO
Mode.
In Non-FIFO Mode, the Transmit Data Request Interrupt Enable allows interrupts to be
generated to the IXP42X product line and IXC1100 control plane processors’ Interrupt
Controller and captured in the UART Interrupt Identification Register (IIR), when the
Transmit Holding Register is empty. Reading the Interrupt Identification Register or
writing a new character into the Transmit Holding Register clears the Transmit Data
Request Interrupt.
In FIFO Mode, the Transmit Data Request Interrupt Enable allows interrupts to be
generated to the IXP42X product line and IXC1100 control plane processors’ Interrupt
Controller and captured in the UART Interrupt Identification Register (IIR), when the
Transmit FIFO is half empty or less.
The Transmit FIFO size is 64 characters. When 32 or fewer characters are remaining in
the Transmit FIFO to be transmitted, the Transmit Data Request Interrupt will be
generated. Reading the Interrupt Identification Register — or writing a new data into
the Transmit FIFO — clears the Transmit Data Request Interrupt.
The Modem Status Interrupt Enable allows interrupts to be generated to the IXP42X
product line and IXC1100 control plane processors Interrupt Controller — and captured
in the UART Interrupt Identification Register (IIR) — when the Clear-to-Send, Data-
Set-Ready, Ring-Indicator, or Received-Line Signal Detect bits in the Modem Status
Register are set to logic 1. Reading the Modem Status Register clears the Modem
Status Interrupt.
Clearing the appropriate bit of the Interrupt-Enable Register may disable each of the
interrupt types previously described. Similarly, by setting the appropriate bits, selected
interrupts can be enabled on a per-interrupt basis.
When the UART interrupts are disabled, the UART is placed into polled mode of
operation. Since the UART receiver and the UART transmitter are controlled separately,
either one or both interfaces can be placed in the polled mode of operation.
In the polled mode of operation, software routines running on the Intel XScale
processor checks receiver and transmitter status via the Line Status Register. Line
Status Register bit 0 will be logic 1, when a character is available to be read from the
(1/ ((1200characters/second)/12characters))) * 4
characters =
= 0.040 seconds
= 40 ms