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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 91
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
3.6.4.1 Global Enable Bit (GE)
The Global Enable bit disables and enables all debug functionality (except the reset
vector trap). Following a processor reset, this bit is clear so all debug functionality is
disabled. When debug functionality is disabled, the BKPT instruction becomes a loop
and external debug breaks, hardware breakpoints, and non-reset vector traps are
ignored.
3.6.4.2 Halt Mode Bit (H)
The Halt Mode bit configures the debug unit for either halt mode or monitor mode.
21 Read-undefined / Write-As-Zero Reserved
undefined undefined
20
SW Read Only
JTAG Read / Write
Trap Data Abort (TD)
unchange
d
0
19
SW Read Only
JTAG Read / Write
Trap Prefetch Abort (TA)
unchange
d
0
18
SW Read Only
JTAG Read / Write
Trap Software Interrupt (TS)
unchange
d
0
17
SW Read Only
JTAG Read / Write
Trap Undefined Instruction (TU)
unchange
d
0
16
SW Read Only
JTAG Read / Write
Trap Reset (TR)
unchange
d
0
15:6 Read-undefined / Write-As-Zero Reserved
undefined undefined
5
SW Read / Write
JTAG Read-Only
Sticky Abort (SA)
0
unchange
d
4:2
SW Read / Write
JTAG Read-Only
Method Of Entry (MOE)
000: Processor Reset
001: Instruction Breakpoint Hit
010: Data Breakpoint Hit
011: BKPT Instruction Executed
100: External Debug Event Asserted
101: Vector Trap Occurred
110: Trace Buffer Full Break
111: Reserved
0b000
unchange
d
1
SW Read / Write
JTAG Read-Only
Trace Buffer Mode (M)
0: Wrap around mode
1: fill-once mode
0
unchange
d
0
SW Read / Write
JTAG Read-Only
Trace Buffer Enable (E)
0: Disabled
1: Enabled
0
unchange
d
Table 33. Debug Control and Status Register (DCSR) (Sheet 2 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G
E
H
T
F
T
I
T
D
T
A
T
S
T
U
T
R
S
A
MOE M E
Bits Access Description
Reset
Value
TRST
Value