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Developer’s Manual March, 2003 8-1
System Management
8
This chapter describes the clocking and power management features of the Intel
®
80200 processor
based on Intel
®
XScale
™
microarchitecture (compliant with the ARM* Architecture V5TE) along
with reset details. Main features include a software controlled internal clock frequency and two low
power modes:
• idle
• sleep
8.1 Clocking
CLK is the input reference clock for the Intel
®
80200 processor. CLK accepts an input clock
frequency of 33 to 66 MHz. The Intel
®
80200 processor uses an internal PLL to lock to the input
clock and multiplies the frequency by a variable multiplier to produce a high-speed core clock
(CCLK). This multiplier is initially configured by the PLL configuration pin (PLLCFG) and can be
changed anytime later by software.Table 8-1 shows the possible clock multipliers immediately
after the reset sequence. PLLCFG can select between a multiplier of three and six. PLLCFG is
sampled when RESET# transitions from low to high.
MCLK is the input memory clock for the Intel
®
80200 processor. MCLK is asynchronous with
respect to CCLK and supports frequencies up to 100 MHz. The ratio of MCLK to CCLK must be
1:3 or less. For example, if CCLK is 200 MHz, MCLK is restricted to 66 MHz or less.
Normally, CLK and MCLK support 40%/60% duty cycle inputs. At higher input frequencies,
MCLK may impose a stricter requirement, such as 50%/50%. See the latest Intel
®
80200
Processor based on Intel
®
XScale
™
Datasheet for details.
Software has the ability to change the frequency of CCLK without having to reset the core. This
feature allows software to conserve power by matching the core frequency to the current workload.
Register CCLKCFG (see Section 7.3.3, “Registers 6-7: Clock and Power Management” on
page 7-21) controls the clock multiplier.
Table 8-1. Reset CCLK Configuration
PLLCFG Value
(Sampled at Deassertion of RESET#)
Initial CLK Multiplier
03
16
a
a. Lower speed grade parts may not provide this; instead they substitute the highest supported multiplier.