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Developer’s Manual March, 2003 10-9
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
10.2.5 Multimaster Support
Simple multimaster support is supplied with the Hold pin. The Hold pin causes the Intel
®
80200
processor to stop issuing new requests as soon as possible (see below for timing) and to float the
following pins: A, ADS#/LEN[2], W/R#/LEN[0], and Lock/LEN[1]. Before floating ADS#, the
Intel
®
80200 processor drives it to an inactive state (high).
Simultaneously with floating the affected signals, the Intel
®
80200 processor asserts HldA.
When HldA is asserted, it is up to the chipset to make sure that the floating signals are driven or
sustained.
Once asserted, the level on the Hold pin must be maintained until HldA has been asserted by the
Intel
®
80200 processor. If Hold is deasserted before HldA asserts, the results are unpredictable.
The delay to asserted HldA after Hold is sampled may vary depending on the state of the bus. If
Hold is asserted on clock edge n, the Intel
®
80200 processor guarantees it asserts HldA by clock
edge n+6.
The Intel
®
80200 processor drives the floated signals two cycles after Hold is deasserted. That is,
if Hold is deasserted at clock edge n, then the Intel
®
80200 processor drives the floating signals to
a valid level on clock edge n+2. The implication of this is that the signals are not carrying valid
data that may be sampled until clock edge n+3. HldA is deasserted at the same time the signals are
taken out of float.
Once Hlda is deasserted, external hardware must wait at least one cycle before asserting Hold
again. That is, Hold may only be asserted at cycle n if Hlda is not asserted at cycle n-1.
If the Intel
®
80200 processor is in a low power mode (see Section 8.3, “Power Management” on
page 8-5) then the timing for entering and exiting hold mode may be faster than described above. If
Hold functionality is desired during one of these modes, the MCLK clock must be toggling.
During reset, the Intel
®
80200 processor honors requests for Hold.
Note that the data bus is not affected at all by the Hold pin or the floating of the request bus. While
the Intel
®
80200 processor is held off the issue bus, data can continue to be returned to the Intel
®
80200 processor on the data bus, and write data can be requested from the Intel
®
80200 processor
by the memory controller. When write data is not being requested by the chipset from the Intel
®
80200 processor, the Intel
®
80200 processor automatically floats the data bus and associated
signals: D, BE#, DCB. This means that write data from another master or read data to another
master can be driven onto the data buses without informing or requesting permission from the
Intel
®
80200 processor. The chipset owns the data bus and completely controls who gets to drive it.
Care must be taken, however, to not assert the Intel
®
80200 processor DValid pin any time other
than two cycles before the next valid Intel
®
80200 processor data cycle.
This system allows memory accesses from the Intel
®
80200 processor to be pipelined with
memory accesses from another master. An Intel
®
80200 processor memory access can be issued,
followed by a memory access from another master, followed by another Intel
®
80200 processor
memory access, all before the data cycles of the first access begin. The data cycles for those
transactions can then occur sequentially (except for any required turnaround cycles) on the data
busses. This would of course require that the other master and the chipset supported this pipelining.