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13-40 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
An external host should take the following steps to load code into the instruction cache following a
cold reset:
• Assert the RESET# and TRST# pins: This resets the JTAG IR to IDCODE and invalidates the
instruction cache (main and mini).
• Load the SELDCSR JTAG instruction into JTAG IR and scan in a value to set the Halt Mode
bit in DCSR and to set the hold_rst signal. For details of the SELDCSR, refer to
Section 13.11.2.
• After hold_rst is set, de-assert the RESET# pin. Internally the processor remains held in reset.
• After RESET# is de-asserted, wait 2030 TCKs.
• Load the LDIC JTAG instruction into JTAG IR.
• Download code into instruction cache in 33-bit packets as described in Section 13.14.3, LDIC
Cache Functions.
• After code download is complete, clock a minimum of 15 TCKs following the last update_dr
in LDIC mode.
• Place the SELDCSR JTAG instruction into the JTAG IR and scan in a value to clear the
hold_rst signal. The Halt Mode bit must remain set to prevent the instruction cache from being
invalidated.
• When hold_rst is cleared, internal reset is de-asserted, and the processor executes the reset
vector at address 0.
An additional issue for debug is setting up the reset vector trap. This must be done before the
internal reset signal is de-asserted. As described in Section 13.4.3, the Halt Mode and the Trap
Reset bits in the DCSR must be set prior to de-asserting reset in order to trap the reset vector. There
are two possibilities for setting up the reset vector trap:
• The reset vector trap can be set up before the instruction cache is loaded by scanning in a
DCSR value that sets the Trap Reset bit in addition to the Halt Mode bit and the hold_rst
signal; OR
• The reset vector trap can be set up after the instruction cache is loaded. In this case, the DCSR
should be set up to do a reset vector trap, with the Halt Mode bit and the hold_rst signal
remaining set.
In either case, when the debugger clears the hold_rst bit to de-assert internal reset, the debugger
must set the Halt Mode and Trap Reset bits in the DCSR.