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Developer’s Manual March, 2003 7-9
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Configuration
7.2.3 Register 2: Translation Table Base Register
7.2.4 Register 3: Domain Access Control Register
7.2.5 Register 4: Reserved
Register 4 is reserved. Reading and writing this register yields unpredictable results.
Table 7-8. Translation Table Base Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Translation Table Base
reset value: unpredictable
Bits Access Description
31:14 Read / Write
Translation Table Base - Physical address of the base of
the first-level table
13:0 Read-unpredictable / Write-as-Zero Reserved
Table 7-9. Domain Access Control Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
reset value: unpredictable
Bits Access Description
31:0 Read / Write
Access permissions for all 16 domains - The meaning
of each field can be found in the
ARM Architecture
Reference Manual
.